79ee5a876f
A glitch was observed if a GPIO PIN was configured to a non-default state by ROM and then Zephyr programs the pin for the same configuration. Root cause is GPIO hardware implementing two output bits for each pin. The alternate output bit is in the pin control register and is r/w by default. The other bit exists in the GPIO parallel ouput register and is read-only by default. The hardware actually reflects the pin's output value into both bits. The fix is to configure the pin with alternate output bit read-write and the last step is to disable alternate output which enabled read-write of the parallel bit. GPIO API's can then use the GPIO parallel out registers. Add logic to return an error from the GPIO interrupt configure API if a pin is not configured as an input. Hardware only performs interrupt detection if the input pad is enabled. Hardware supports a pin being configured for both input and output. Applications should add the GPIO_INPUT flag to all pin configuration requiring interrupt detection. The interpretation of input and output flags for the get configuration API appears to be only one of the flags can be set. Please refer to the GPIO driver tests. Updated GPIO interrupt configure to clear the input pad disable bit due to interrupt detection HW is connected only to input side of pin. Signed-off-by: Manimaran A <manimaran.a@microchip.com> |
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| .. | ||
| gpio_api_1pin | ||
| gpio_basic_api | ||
| gpio_enable_disable_interrupt | ||
| gpio_get_direction | ||
| gpio_hogs | ||