96 lines
2.4 KiB
YAML
96 lines
2.4 KiB
YAML
# Copyright (c) 2018, NXP
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# SPDX-License-Identifier: Apache-2.0
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description: NXP Kinetis DSPI controller
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compatible: "nxp,kinetis-dspi"
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include: ["spi-controller.yaml", "pinctrl-device.yaml"]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clocks:
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required: true
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pcs-sck-delay:
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type: int
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required: false
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description: |
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Delay in nanoseconds from the chip select assert to the first clock
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edge. If not set, the minimum supported delay is used.
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sck-pcs-delay:
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type: int
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required: false
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description: |
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Delay in nanoseconds from the last clock edge to the chip select
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deassert. If not set, the minimum supported delay is used.
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transfer-delay:
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type: int
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required: false
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description: |
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Delay in nanoseconds from the chip select deassert to the next chip
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select assert. If not set, the minimum supported delay is used.
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pinctrl-0:
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type: phandles
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required: true
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nxp,rx-tx-chn-share:
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type: boolean
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required: false
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description: If the edma channel shared with tx and rx
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ctar:
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type: int
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required: false
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description: |
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ctar register selection range form 0-1 for master mode, 0 for slave mode
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sample-point:
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type: int
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required: false
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description: |
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Controls when the DSPI master samples SIN in the Modified Transfer Format.
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This field is valid only when the CPHA bit in the CTAR register is 0.
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continuous-sck:
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type: boolean
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required: false
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description: |
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continuous SCK enable. Note that the continuous SCK is only
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supported for CPHA = 1.
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rx-fifo-overwrite:
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type: boolean
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required: false
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description: |
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receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
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data is ignored and the data from the transfer that generated the overflow
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is also ignored. If ROOE = 1, the incoming data is shifted to the
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shift register.
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modified-timing-format:
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type: boolean
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required: false
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description: |
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Enables a modified transfer format to be used if true.
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tx-fifo-size:
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type: int
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required: false
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description: |
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tx fifo size
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rx-fifo-size:
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type: int
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required: false
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description: |
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rx fifo size
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