178 lines
4.7 KiB
C
178 lines
4.7 KiB
C
/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32WB0 processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_system.h>
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#include <stm32_ll_radio.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/toolchain.h>
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#include <cmsis_core.h>
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#include <stdint.h>
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#include <system_stm32wb0x.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(soc);
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/**
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* CMSIS System Core Clock: global variable holding the system core clock,
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* which is the frequency supplied to the SysTick timer and processor core.
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*
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* On STM32WB0 series, after RESET, the system clock frequency is 16MHz.
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*/
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uint32_t SystemCoreClock = 16000000U;
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/**
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* RAM Virtual Register: special structure located at the start
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* of SRAM0; used by the UART bootloader and the Low Power Manager.
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* Data type definition comes from @ref system_stm32wb0xx.h
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*/
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Z_GENERIC_SECTION("stm32wb0_RAM_VR")
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__used RAM_VR_TypeDef RAM_VR;
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/** Power Controller node (shorthand for upcoming macros) */
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#define PWRC DT_INST(0, st_stm32wb0_pwr)
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/* Convert DTS properties to LL macros */
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#define SMPS_PRESCALER _CONCAT(LL_RCC_SMPS_DIV_, DT_PROP(PWRC, smps_clock_prescaler))
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#if SMPS_MODE != STM32WB0_SMPS_MODE_OFF
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BUILD_ASSERT(DT_NODE_HAS_PROP(PWRC, smps_bom),
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"smps-bom must be specified");
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#define SMPS_BOM \
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_CONCAT(LL_PWR_SMPS_BOM, DT_PROP(PWRC, smps_bom))
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#define SMPS_LP_MODE \
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COND_CODE_1( \
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DT_PROP(PWRC, smps_lp_floating), \
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(LL_PWR_SMPS_LPOPEN), \
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(LL_PWR_NO_SMPS_LPOPEN))
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#if defined(PWR_CR5_SMPS_PRECH_CUR_SEL)
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#define SMPS_CURRENT_LIMIT \
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_CONCAT(LL_PWR_SMPS_PRECH_LIMIT_CUR_, \
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DT_STRING_UNQUOTED(PWRC, smps_current_limit))
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#endif /* PWR_CR5_SMPS_PRECH_CUR_SEL */
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#define SMPS_OUTPUT_VOLTAGE \
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_CONCAT(LL_PWR_SMPS_OUTPUT_VOLTAGE_, \
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DT_STRING_UNQUOTED(PWRC, smps_output_voltage))
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#endif /* SMPS_MODE != STM32WB0_SMPS_MODE_OFF */
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static void configure_smps(void)
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{
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/* Configure SMPS clock prescaler */
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LL_RCC_SetSMPSPrescaler(SMPS_PRESCALER);
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#if SMPS_MODE == STM32WB0_SMPS_MODE_OFF
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/* Disable SMPS */
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LL_PWR_SetSMPSMode(LL_PWR_NO_SMPS);
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while (LL_PWR_IsSMPSReady()) {
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/* Wait for SMPS to turn off */
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}
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#else
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/* Select correct BOM */
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LL_PWR_SetSMPSBOM(SMPS_BOM);
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/* Configure low-power mode */
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LL_PWR_SetSMPSOpenMode(SMPS_LP_MODE);
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/* Enable SMPS */
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LL_PWR_SetSMPSMode(LL_PWR_SMPS);
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while (!LL_PWR_IsSMPSReady()) {
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/* Wait for SMPS to turn on */
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}
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/* Place SMPS in PRECHARGE (BYPASS) mode.
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* This is required to change SMPS output voltage,
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* so we can do it unconditionally.
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*/
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LL_PWR_SetSMPSPrechargeMode(LL_PWR_SMPS_PRECHARGE);
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while (LL_PWR_IsSMPSinRUNMode()) {
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/* Wait for SMPS to enter PRECHARGE mode */
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}
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if (SMPS_MODE == STM32WB0_SMPS_MODE_PRECHARGE) {
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#if defined(PWR_CR5_SMPS_PRECH_CUR_SEL)
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/**
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* SMPS should remain in PRECHARGE mode.
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* We still have to configure the output current
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* limit specified in Device Tree, though this
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* can only be done if this SoC supports it.
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*/
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LL_PWR_SetSMPSPrechargeLimitCurrent(SMPS_CURRENT_LIMIT);
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#endif /* PWR_CR5_SMPS_PRECH_CUR_SEL */
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} else {
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/**
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* SMPS mode requested is RUN mode. Configure the output
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* voltage to the desired value then exit PRECHARGE mode.
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*/
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LL_PWR_SMPS_SetOutputVoltageLevel(SMPS_OUTPUT_VOLTAGE);
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/* Exit PRECHARGE mode (returns in RUN mode) */
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LL_PWR_SetSMPSPrechargeMode(LL_PWR_NO_SMPS_PRECHARGE);
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while (!LL_PWR_IsSMPSinRUNMode()) {
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/* Wait for SMPS to enter RUN mode */
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}
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}
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#endif /* SMPS_MODE == STM32WB0_SMPS_MODE_OFF */
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}
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning,
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* so the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32wb0_init(void)
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{
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/* Update CMSIS SystemCoreClock variable (CLK_SYS) */
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/* On reset, the 64MHz HSI is selected as input to
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* the SYSCLKPRE prescaler, set to 4, resulting in
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* CLK_SYS being equal to 16MHz.
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*/
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SystemCoreClock = 16000000U;
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/* Remap address 0 to user flash memory */
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LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH);
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/**
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* Save application exception vector address in RAM_VR.
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* By now, SCB->VTOR should point to _vector_table,
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* so use that value instead of _vector_table directly.
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*/
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RAM_VR.AppBase = SCB->VTOR;
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/* Enable retention of all RAM banks in Deepstop */
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LL_PWR_EnableRAMBankRet(LL_PWR_RAMRET_1);
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#if defined(LL_PWR_RAMRET_2)
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LL_PWR_EnableRAMBankRet(LL_PWR_RAMRET_2);
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#endif
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#if defined(LL_PWR_RAMRET_3)
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LL_PWR_EnableRAMBankRet(LL_PWR_RAMRET_3);
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#endif
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/* Configure SMPS step-down converter */
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configure_smps();
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return 0;
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}
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SYS_INIT(stm32wb0_init, PRE_KERNEL_1, 0);
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