123 lines
3.4 KiB
Plaintext
123 lines
3.4 KiB
Plaintext
# Nordic Semiconductor nRF52 MCU line
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# Copyright (c) 2016-2023 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_NRF52X
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select ARM
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select SOC_COMPATIBLE_NRF52X
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select CPU_CORTEX_M4
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select CPU_HAS_ARM_MPU
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imply XIP
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select HAS_NRFX
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select HAS_NORDIC_DRIVERS
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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select HAS_SWO
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select HAS_POWEROFF
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config SOC_NRF52832
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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config SOC_NRF52833
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select SOC_COMPATIBLE_NRF52833
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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config SOC_NRF52840
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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if SOC_SERIES_NRF52X
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config SOC_DCDC_NRF52X
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bool
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select DEPRECATED
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help
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This option is deprecated, use devicetree instead. Example
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configuration:
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®/reg1 {
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regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
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};
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Enable nRF52 series System on Chip DC/DC converter.
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config SOC_DCDC_NRF52X_HV
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bool
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depends on SOC_NRF52840_QIAA
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select DEPRECATED
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help
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This option is deprecated, use devicetree instead. Example
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configuration:
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®0 {
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status = "okay";
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};
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Enable nRF52 series System on Chip High Voltage DC/DC converter.
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config GPIO_AS_PINRESET
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bool "[DEPRECATED] GPIO as pin reset (reset button)"
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select DEPRECATED
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help
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This option is deprecated, use devicetree instead. Example
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configuration:
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&uicr {
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gpio-as-nreset;
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};
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config NRF_ENABLE_ICACHE
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bool "The instruction cache (I-Cache)"
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depends on SOC_NRF52832 || SOC_NRF52833 || SOC_NRF52840
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default y
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config NRF52_ANOMALY_132_DELAY_US
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int "Anomaly 132 workaround delay (microseconds)"
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default 330
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range 0 330
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depends on NRF52_ANOMALY_132_WORKAROUND
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help
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Due to Anomaly 132 LF RC source may not start if restarted in certain
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window after stopping (230 us to 330 us). Software reset also stops the
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clock so if clock is initiated in certain window, the clock may also fail
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to start at reboot. A delay is added before starting LF clock to ensure
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that anomaly conditions are not met. Delay should be long enough to ensure
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that clock is started later than 330 us after reset. If crystal oscillator
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(XO) is used then low frequency clock initially starts with RC and then
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seamlessly switches to XO which has much longer startup time thus,
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depending on application, workaround may also need to be applied.
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Additional drivers initialization increases initialization time and delay
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may be shortened. Workaround is disabled by setting delay to 0.
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config NRF52_ANOMALY_198_WORKAROUND
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bool "Anomaly 198 workaround"
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default y
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depends on SOC_NRF52840
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depends on NRFX_SPIM3
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help
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This anomaly applies to IC revisions "Engineering B" up to "3", the most
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recent one.
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config NRF52_ANOMALY_109_WORKAROUND
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bool "Anomaly 109 workaround"
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default y
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depends on SOC_NRF52832
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depends on NRFX_SPIS || NRFX_SPIM || NRFX_TWIM || NRFX_PWM
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help
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Due to Anomaly 109 the first byte sent out by these peripherals is
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sometimes wrong. This occurs when the system enters IDLE and stops the
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64MHz clock at the same time as the peripheral that is using DMA is started.
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This anomaly applies to IC revisions up to "3", the most recent one.
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config NRF52_ANOMALY_109_WORKAROUND_EGU_INSTANCE
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int "Anomaly 109 workaround EGU instance"
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depends on NRF52_ANOMALY_109_WORKAROUND
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range 0 5
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default 5
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help
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EGU instance used by the nRF52 Anomaly 109 workaround for PWM.
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endif # SOC_SERIES_NRF52X
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