65 lines
1.6 KiB
C
65 lines
1.6 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the ARM LTD Beetle SoC PLL.
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*
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*/
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#ifndef _ARM_BEETLE_SOC_PLL_H_
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#define _ARM_BEETLE_SOC_PLL_H_
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/*
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* This header provides the defines to configure the Beetle PLL.
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*
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* BEETLE PLL main register is the PLLCTRL in the System Control
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*
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* The PLLCTRL relevant bits are:
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* - PLL_OUTPUTDIV [9:8]
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* - PLL_INPUTDIV [20:16]
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* - PLL_FEEDDIV [30:24]
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*
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* The formula to calculate the output frequency of the PLL is:
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* Fout = Fin * PLL_FEEDDIV / (PLL_INPUTDIV * PLL_OUTPUTDIV)
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* The Fin = 24Mhz on Beetle
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*
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* PLL_OUTPUTDIV | 0 1 2 3
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* -----------------------
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* | 1 2 4 8
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*
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* PLL_INPUTDIV = R[20:16] + 1
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*
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* PLL_FEEDDIV = 2*(R[30:24] + 1)
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*
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* BEETLE PLL has a non bypassable divider by 2 in output
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*
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* BEETLE PLL derived clock is prescaled [1-16]
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*/
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/* BEETLE PLL Masks */
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#define PLL_MAINCLK_ENABLE_Msk 0x1
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#define PLL_MAINCLK_DISABLE_Msk 0x1
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#define PLL_MAINCLK_PRESCALER_Msk 0xF0
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/* BEETLE PLL Configuration */
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#define BEETLE_PLL_CONFIGURATION 0x17000200
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/* BEETLE PLL Supported Frequencies */
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/* BEETLE_PLL_48Mhz */
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#define BEETLE_PLL_FREQUENCY_48MHZ 48000000
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#define BEETLE_PLL_PRESCALER_48MHZ 0x21
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/* BEETLE_PLL_36Mhz */
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#define BEETLE_PLL_FREQUENCY_36MHZ 36000000
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#define BEETLE_PLL_PRESCALER_36MHZ 0x31
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/* BEETLE_PLL_24Mhz */
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#define BEETLE_PLL_FREQUENCY_24MHZ 24000000
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#define BEETLE_PLL_PRESCALER_24MHZ 0x51
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/* BEETLE_PLL_12Mhz */
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#define BEETLE_PLL_FREQUENCY_12MHZ 12000000
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#define BEETLE_PLL_PRESCALER_12MHZ 0xB1
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#endif /* _ARM_BEETLE_SOC_PLL_H_ */
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