7fe29dcee9
The i2s_cavs.c driver manipulates cache lines before commencing any DMA transfers. With write-back cache, if the DMA receive buffer is not aligned to the cache lines, the data around the buffer will be invalidated and may never written to memory. Since the driver takes an external memory slab as buffer and there is no easy way to force cache line alignment on the application side, set the cached region to write-through to avoid potential issue. Fixes #13223 Signed-off-by: Daniel Leung <daniel.leung@intel.com> |
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| .. | ||
| D_108mini | ||
| D_212GP | ||
| D_233L | ||
| XRC_D2PM_5swIrq | ||
| XRC_FUSION_AON_ALL_LM | ||
| esp32 | ||
| hifi2_std | ||
| hifi3_bd5 | ||
| hifi3_bd5_call0 | ||
| hifi4_bd7 | ||
| hifi_mini | ||
| hifi_mini_4swIrq | ||
| intel_s1000 | ||
| sample_controller | ||