117 lines
2.9 KiB
Plaintext
117 lines
2.9 KiB
Plaintext
/*
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* Copyright (c) 2023 PSICONTROl nv
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u5/stm32u5.dtsi>
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/ {
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soc {
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compatible = "st,stm32u595", "st,stm32u5", "simple-bus";
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pinctrl: pin-controller@42020000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x42020000 0x2800>;
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gpioj: gpio@42022400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42022400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000200>;
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};
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};
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usart6: serial@40006400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40006400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
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resets = <&rctl STM32_RESET(APB1L, 25U)>;
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interrupts = <126 0>;
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status = "disabled";
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};
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i2c5: i2c@40009800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40009800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000040>;
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interrupts = <128 0>, <127 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c6: i2c@40009c00 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40009c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000080>;
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interrupts = <130 0>, <129 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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/* Available in STM32U59x/5Ax/5Fx/5Gx SoCs */
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adc2: adc@42028100 {
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compatible = "st,stm32-adc";
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reg = <0x42028100 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>;
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interrupts = <37 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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resolutions = <STM32_ADC_RES(14, 0x00)
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STM32_ADC_RES(12, 0x01)
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STM32_ADC_RES(10, 0x02)
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STM32_ADC_RES(8, 0x03)>;
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sampling-times = <5 6 12 20 36 68 391 814>;
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st,adc-clock-source = <ASYNC>;
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st,adc-sequencer = <FULLY_CONFIGURABLE>;
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};
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/*
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* Available in STM32U59x/5Ax/5Fx/5Gx SoCs
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* dual mode: adc1 and adc2 coupled
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*/
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adc1_2: adc@42028300 {
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compatible = "st,stm32-adc";
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reg = <0x42028300 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>;
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interrupts = <37 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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resolutions = <STM32_ADC_RES(14, 0x00)
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STM32_ADC_RES(12, 0x01)
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STM32_ADC_RES(10, 0x02)
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STM32_ADC_RES(8, 0x03)>;
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sampling-times = <5 6 12 20 36 68 391 814>;
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st,adc-clock-source = <ASYNC>;
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st,adc-sequencer = <FULLY_CONFIGURABLE>;
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};
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};
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smbus5: smbus5 {
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compatible = "st,stm32-smbus";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c = <&i2c5>;
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status = "disabled";
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};
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smbus6: smbus6 {
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compatible = "st,stm32-smbus";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c = <&i2c6>;
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status = "disabled";
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};
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};
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