zephyr

History

Maureen Helm f646f8d0cf soc: nxp_kinetis: Refactor flash configuration field to a common place Refactors the kinetis flash configuration field so it can be shared across all kinetis SoCs. Defaults are overridden for the k8x and ke1xf series to preserve values used prior to this refactoring. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>		2019-09-13 13:58:46 -05:00
..
CMakeLists.txt	…
Kconfig.defconfig.mk64f12	drivers: pwm: mcux_ftm: use device tree for obtaining clock frequency	2019-08-09 07:32:43 -05:00
Kconfig.defconfig.series	…
Kconfig.series	…
Kconfig.soc	soc: nxp: k6x: Add CAN support	2019-06-26 16:05:51 -05:00
README.txt	…
dts_fixup.h	drivers: pwm: mcux_ftm: use device tree for obtaining clock frequency	2019-08-09 07:32:43 -05:00
linker.ld	soc: nxp_kinetis: Make kinetis flash configuration field configurable	2019-09-13 13:58:46 -05:00
nxp_mpu_regions.c	soc: k64f MPU configured to always allow USB	2019-07-30 13:08:43 +03:00
soc.c	soc: nxp_kinetis: Refactor flash configuration field to a common place	2019-09-13 13:58:46 -05:00
soc.h	soc/arm/nxp*: rearrange for standard use of extern "C"	2019-08-20 00:49:15 +02:00
wdog.S	…

README.txt

Notes on the FSL FRDM K64F SRAM base address and size

Although the K64F CPU has 64 kB of SRAM at 0x1FFF0000 (code space), it is not
used by the FSL FRDM K64F platform.  Only the 192 kB region based at the
standard ARMv7-M SRAM base address of 0x20000000 is supported.

As such the following values are used:

CONFIG_SRAM_BASE_ADDRESS=0x20000000
CONFIG_SRAM_SIZE=64      # Measured in kB