f8a909dad1
Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Note that this does not enable TLS for all Xtensa SoC. This is because Xtensa SoCs are highly configurable so that each SoC can be considered a whole architecture. So TLS needs to be enabled on the SoC level, instead of at the arch level. Signed-off-by: Daniel Leung <daniel.leung@intel.com> |
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| .. | ||
| offsets | ||
| startup | ||
| CMakeLists.txt | ||
| atomic.S | ||
| cpu_idle.c | ||
| crt1.S | ||
| fatal.c | ||
| irq_manage.c | ||
| irq_offload.c | ||
| tls.c | ||
| window_vectors.S | ||
| xtensa-asm2-util.S | ||
| xtensa-asm2.c | ||
| xtensa_intgen.py | ||
| xtensa_intgen.tmpl | ||