Andrew Boie edc5e31d6b x86_64: fix RBX clobber in nested IRQ case ... In the code path for nested interrupts, we are not saving RBX, yet the assembly code is using it as a storage location for the ISR. Use RAX. It is backed up in both the nested and non-nested cases, and the ASM code is not currently using it at that point. Fixes: #29594 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>		2020-10-28 10:29:32 -07:00
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core	x86_64: fix RBX clobber in nested IRQ case	2020-10-28 10:29:32 -07:00
include	x86: add support for thread local storage	2020-10-24 10:52:00 -07:00
zefi	arch/x86: Make EFI copies bytewise	2020-10-13 14:07:24 -07:00
CMakeLists.txt	timing: add support for x86	2020-09-05 13:28:38 -05:00
Kconfig	x86: paging code rewrite	2020-08-25 15:49:59 -04:00
gen_gdt.py	x86: add support for thread local storage	2020-10-24 10:52:00 -07:00
gen_idt.py	x86: gen_idt.py: typo fix	2020-05-21 14:44:33 +02:00
gen_mmu.py	mmu: support only identity RAM mapping	2020-09-03 14:24:38 -04:00
ia32.cmake	x86: add build system hooks for page tables	2020-08-25 15:49:59 -04:00
intel64.cmake	x86: add build system hooks for page tables	2020-08-25 15:49:59 -04:00
timing.c	timing: add support for x86	2020-09-05 13:28:38 -05:00