88 lines
1.9 KiB
ArmAsm
88 lines
1.9 KiB
ArmAsm
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief CPU power management
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*
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* CPU power management routines.
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*/
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#define _ASMLANGUAGE
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#include <nano_private.h>
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#include <offsets.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <arch/cpu.h>
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GTEXT(nano_cpu_idle)
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GTEXT(nano_cpu_atomic_idle)
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GDATA(nano_cpu_sleep_mode)
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#if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
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GTEXT(_power_save_idle)
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#endif
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SECTION_VAR(BSS, nano_cpu_sleep_mode)
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.word 0
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#if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
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.macro enter_tickless_idle
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/* interrupts are locked when entering here */
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push_s blink
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jl _power_save_idle
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pop_s blink
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.endm
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#else
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#define enter_tickless_idle
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#endif
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/*
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* @brief Put the CPU in low-power mode
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*
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* This function always exits with interrupts unlocked.
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*
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* void nanCpuIdle(void)
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*/
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SECTION_FUNC(TEXT, nano_cpu_idle)
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enter_tickless_idle
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ld r1, [nano_cpu_sleep_mode]
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or r1, r1, (1 << 4) /* set IRQ-enabled bit */
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sleep r1
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j_s.nd [blink]
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nop
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/*
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* @brief Put the CPU in low-power mode, entered with IRQs locked
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*
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* This function exits with interrupts restored to <key>.
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*
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* void nano_cpu_atomic_idle(unsigned int key)
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*/
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SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
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enter_tickless_idle
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ld r1, [nano_cpu_sleep_mode]
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or r1, r1, (1 << 4) /* set IRQ-enabled bit */
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sleep r1
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j_s.d [blink]
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seti r0
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