209 lines
6.2 KiB
YAML
209 lines
6.2 KiB
YAML
# Copyright 2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: |
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NXP S32 Quad Serial Peripheral Interface (QSPI) Controller.
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QSPI acts as an interface to up to two serial flash memory devices, each with
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up to eight bidirectional bidirectional data lines, depending on the platform.
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compatible: "nxp,s32-qspi"
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include: [base.yaml, pinctrl-device.yaml]
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bus: qspi
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properties:
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reg:
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required: true
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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data-rate:
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type: string
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enum:
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- SDR
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- DDR
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description: |
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Selects the read mode:
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- Single Data Rate (SDR): sampling of incoming data occurs on single edges.
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- Double Data Rate (DDR): sampling of incoming data occurs on both edges.
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hold-time-2x:
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type: boolean
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description: |
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Set to align incoming data with 2x serial flash half clock, when in DDR
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mode. Otherwise, data will be aligned to the posedge of the controller's
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internal reference clock.
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sample-delay-half-cycle:
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type: boolean
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description: |
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Set to use half-cycle early DQS delay when sampling received data.
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sample-phase-inverted:
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type: boolean
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description: |
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Set to sample received data at inverted clock.
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cs-setup-time:
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type: int
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default: 3
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description: |
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Chip select setup time, in serial clock cycles. A bigger value will pull
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the CS signal earlier before the transaction starts.
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The default corresponds to the reset value of the register field.
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cs-hold-time:
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type: int
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default: 3
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description: |
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Chip select hold time, in serial clock cycles. A bigger value will release
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the CS signal later after the transaction ends.
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The default corresponds to the reset value of the register field.
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column-space:
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type: int
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default: 0
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description: |
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Column Address Space bit width. For example, if the column address is
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[2:0] of QSPI_SFAR/AHB address, then the column address space bit width
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must be 3. If there is no column address separation in any serial flash
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device connected to this controller, this value must be programmed to 0.
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The default corresponds to the reset value of the register field.
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word-addressable:
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type: boolean
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description: |
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Set if the serial flash device connected to this controller is word
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(2 bytes) addressable.
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byte-swapping:
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type: boolean
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description: |
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In case of Octal DDR mode, specifies whether a word unit composed of two
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bytes from posedge and negedge of a single DQS cycle needs to be swapped.
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ahb-buffers-masters:
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type: array
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description: |
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Masters ID's for the AHB receive buffers. The master ID of every incoming
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request is checked and the data is returned or fetched into the
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corresponding associated buffer. The maximum number of buffers is SoC
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specific.
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ahb-buffers-sizes:
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type: array
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description: |
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Sizes (in bytes) of the AHB receive buffers. The maximum buffer size and
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maximum number of buffers is SoC specific.
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ahb-buffers-all-masters:
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type: boolean
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description: |
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Any access from a master not associated with any other buffer is routed to
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the last buffer.
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a-rx-clock-source:
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type: string
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enum:
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- LOOPBACK
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- LOOPBACK DQS
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- INTERNAL DQS
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- EXTERNAL DQS
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description: |
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Selects DQS clock source for sampling read data at side A:
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- LOOPBACK: use loopback clock from dummy internal PAD as strobe signal.
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- LOOPBACK DQS: use loopback clock from PAD as strobe signal.
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- INTERNAL DQS: use internally generated strobe signal.
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- EXTERNAL DQS: use external strobe signal.
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a-io2-idle-high:
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type: boolean
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description: |
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Set if the logic level of IO2 signal output of this controller must be
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driven high in the inactive state.
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This property applies to side A of the controller.
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a-io3-idle-high:
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type: boolean
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description: |
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Set if the logic level of IO3 signal output of this controller must be
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driven high in the inactive state.
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This property applies to side A of the controller.
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a-dll-mode:
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type: string
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enum:
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- BYPASSED
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- MANUAL UPDATE
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- AUTO UPDATE
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default: BYPASSED
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description: |
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DLL mode. The supported modes depends on the SoC.
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This property applies to side A of the controller.
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a-dll-freq-enable:
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type: boolean
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description: |
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Selects delay-chain for high frequency of operation.
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This property applies to side A of the controller.
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a-dll-ref-counter:
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type: int
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enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
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default: 1
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description: |
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Select the "n+1" interval of DLL phase detection and reference delay
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updating interval.
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Minimum recommended value is 1 (reset value).
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This property applies to side A of the controller.
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a-dll-resolution:
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type: int
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enum: [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
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default: 2
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description: |
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Minimum resolution for DLL phase detector to remain locked/unlocked based
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on flash memory clock jitter.
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The minimum value is 2 (reset value).
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This property applies to side A of the controller.
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a-dll-coarse-delay:
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type: int
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enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
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default: 0
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description: |
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This field sets the number of delay elements in each delay tap. The field
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is used to overwrite DLL-generated delay values.
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Default to 0 (reset value).
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This property applies to side A of the controller.
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a-dll-fine-delay:
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type: int
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enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
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default: 0
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description: |
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This field sets the number of fine offset delay elements up to 16 in
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incoming DQS.
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Default to 0 (reset value).
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This property applies to side A of the controller.
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a-dll-tap-select:
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type: int
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enum: [0, 1, 2, 3, 4, 5, 6, 7]
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default: 0
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description: |
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Selects the Nth tap provided by the slave delay-chain.
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Default to 0 (reset value).
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This property applies to side A of the controller.
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child-binding:
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description: NXP S32 QuadSPI port
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include: nxp,s32-qspi-device.yaml
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