66 lines
1.5 KiB
YAML
66 lines
1.5 KiB
YAML
# Copyright (c) 2023, STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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PLL node binding for STM32WBA devices
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It can be used to describe PLL1
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This PLL could take one of clk_hse or clk_hsi as input clock, with
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an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
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clock in this acceptable range.
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PLL1 can have up to 3 output clocks and for each output clock, the
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frequency can be computed with the following formula:
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f(PLL_P) = f(VCO clock) / PLLP
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f(PLL_Q) = f(VCO clock) / PLLQ
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f(PLL_R) = f(VCO clock) / PLLR
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with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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Note: VCOx frequency range is 128 to 544 MHz. To reduce the power consumption,
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it is recommended to configure the VCO to the lowest frequency.
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The PLL output frequency must not exceed 100 MHz.
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compatible: "st,stm32wba-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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clocks:
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required: true
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div-m:
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type: int
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required: true
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description: |
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Prescaler for PLLx
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input clock
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Valid range: 1 - 8
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mul-n:
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type: int
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required: true
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description: |
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PLLx multiplication factor for VCO
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Valid range: 4 - 512
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div-q:
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type: int
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description: |
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PLLx DIVQ division factor
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Valid range: 1 - 128
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div-r:
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type: int
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required: true
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description: |
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PLLx DIVR division factor
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Valid range: 1 - 128
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