80 lines
1.8 KiB
YAML
80 lines
1.8 KiB
YAML
# Copyright (c) 2021, Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
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description: |
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PLL node binding for STM32U5 devices
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It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3.
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These PLLs could take one of clk_hse, clk_hsi or clk_msis as input clock, with
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an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
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clock in this acceptable range.
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Each PLL can have up to 3 output clocks and for each output clock, the
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frequency can be computed with the following formulae:
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f(PLL_P) = f(VCO clock) / PLLP
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f(PLL_Q) = f(VCO clock) / PLLQ
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f(PLL_R) = f(VCO clock) / PLLR
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with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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Note: To reduce the power consumption, it is recommended to configure the VCOx
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clock output to the lowest frequency.
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The PLL output frequency must not exceed 160 MHz.
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compatible: "st,stm32u5-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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clocks:
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required: true
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div-m:
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type: int
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required: true
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description: |
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Prescaler for PLLx
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input clock
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Valid range: 1 - 16
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mul-n:
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type: int
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required: true
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description: |
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PLLx multiplication factor for VCO
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Valid range: 4 - 512
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div-p:
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type: int
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description: |
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PLLx DIVP division factor
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Valid range: 1 - 128
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div-q:
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type: int
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description: |
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PLLx DIVQ division factor
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Valid range: 1 - 128
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div-r:
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type: int
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required: true
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description: |
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PLLx DIVR division factor
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On PLL1, only division by 1 and even division values are allowed.
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No restrictions for PLL2 and PLL3
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Valid range: 1 - 128
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fracn:
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type: int
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description: |
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PLLx FRACN value
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Valid range: 0 - 8191
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