127 lines
2.7 KiB
YAML
127 lines
2.7 KiB
YAML
# Copyright (c) 2021, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 Reset and Clock controller node for STM32H7 devices
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This node is in charge of system clock ('SYSCLK') source selection and
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System Clock Generation.
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Configuring STM32 Reset and Clock controller node:
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System clock source should be selected amongst the clock nodes available in "clocks"
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node (typically 'clk_hse, clk_csi', 'pll', ...).
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As part of this node configuration, SYSCLK frequency should also be defined, using
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"clock-frequency" property.
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Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
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prescaler properties.
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Here is an example of correctly configured rcc node:
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&rcc {
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clocks = <&pll>; /* Set pll as SYSCLK source */
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clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
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d1cpre = <1>;
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hpre = <1>;
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d1ppre = <1>;
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d2ppre1 = <1>;
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d2ppre2 = <1>;
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d3ppre = <1>;
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}
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Confere st,stm32-rcc binding for information about domain clocks configuration.
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compatible: "st,stm32h7-rcc"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#clock-cells":
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const: 2
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clock-frequency:
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required: true
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type: int
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description: |
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default frequency in Hz for clock output
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d1cpre:
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type: int
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required: true
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enum:
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- 1
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description: |
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D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
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lower than SYSCLK frequency (actual core frequency).
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Zephyr doesn't make a difference today between these two clocks.
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Changing this prescaler is not allowed until it is made possible to
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use them independently in Zephyr clock subsystem.
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hpre:
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type: int
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required: true
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description: |
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D2 domain, CPU2 core clock and AHB(1/2/3/4) peripheral prescaler
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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- 64
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- 128
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- 256
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- 512
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d1ppre:
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type: int
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required: true
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description: |
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D1 domain, APB3 peripheral prescaler
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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d2ppre1:
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type: int
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required: true
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description: |
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D2 domain, APB1 peripheral prescaler
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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d2ppre2:
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type: int
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required: true
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description: |
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D2 domain, APB2 peripheral prescaler
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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d3ppre:
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type: int
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required: true
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description: |
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D3 domain, APB4 peripheral prescaler
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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clock-cells:
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- bus
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- bits
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