149 lines
2.7 KiB
Plaintext
149 lines
2.7 KiB
Plaintext
/*
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* Copyright (c) 2024 GARDENA GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m3";
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device_type = "cpu";
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clock-frequency = <20000000>;
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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pinctrl: pinctrl {
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compatible = "silabs,si32-pinctrl";
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status = "okay";
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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pll0: pll0@4003b000 {
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compatible = "silabs,si32-pll";
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#clock-cells = <0>;
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reg = <0x4003b000>;
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status = "disabled";
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};
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clk_ahb: clk-ahb {
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compatible = "silabs,si32-ahb";
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#clock-cells = <0>;
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status = "disabled";
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};
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clk_apb: clk-apb {
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compatible = "silabs,si32-apb";
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#clock-cells = <0>;
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divider = <1>;
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clocks = <&clk_ahb>;
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status = "disabled";
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};
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};
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soc {
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dma: dma-controller@40036000 {
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compatible = "silabs,si32-dma";
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reg = <0x40036000 0x1000>;
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interrupts = <4 0>, <5 0>, <6 0>, <7 0>,
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<8 0>, <9 0>, <10 0>, <11 0>,
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<12 0>, <13 0>, <14 0>, <15 0>,
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<16 0>, <17 0>, <18 0>, <19 0>;
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dma-channels = <16>;
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#dma-cells = <3>;
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status = "disabled";
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};
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crypto: crypto@40027000 {
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compatible = "silabs,si32-aes";
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reg = <0x40027000 0x1000>;
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interrupts = <42 0>;
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dmas = <&dma 5 0 0>,
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<&dma 6 0 0>,
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<&dma 7 0 0>;
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dma-names = "tx", "rx", "xor";
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status = "disabled";
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};
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flash: flash-controller@4002e000 {
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compatible = "silabs,si32-flash-controller";
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reg = <0x4002e000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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write-block-size = <2>;
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};
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};
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usart0: usart@40000000 {
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compatible = "silabs,si32-usart";
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reg = <0x40000000 0x1000>;
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interrupts = <27 0>;
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clocks = <&clk_apb>;
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status = "disabled";
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};
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usart1: usart@40001000 {
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compatible = "silabs,si32-usart";
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reg = <0x40001000 0x1000>;
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interrupts = <28 0>;
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clocks = <&clk_apb>;
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status = "disabled";
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};
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gpio0: gpio@4002a0a0 {
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compatible = "silabs,si32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x4002a0a0 0xa0>;
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};
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gpio1: gpio@4002a140 {
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compatible = "silabs,si32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x4002a140 0xa0>;
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};
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gpio2: gpio@4002a1e0 {
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compatible = "silabs,si32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x4002a1e0 0xc0>;
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};
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gpio3: gpio@4002a320 {
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compatible = "silabs,si32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x4002a320 0xa0>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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