455 lines
10 KiB
Plaintext
455 lines
10 KiB
Plaintext
/*
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* Copyright (c) 2020 TriaGnoSys GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <arm/silabs/gpio_gecko.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/pinctrl/gecko-pinctrl.h>
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#include <dt-bindings/adc/adc.h>
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#include <dt-bindings/clock/silabs/xg24-clock.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &msc;
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zephyr,entropy = &se;
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};
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clocks {
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hfxort: hfxort {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfxo>;
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};
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hfrcodpllrt: hfrcodpllrt {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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sysclk: sysclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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hclk: hclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sysclk>;
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/* Divider 1, 2, 4, 8, or 16 */
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clock-div = <1>;
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};
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pclk: pclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hclk>;
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/* Divider 1 or 2 */
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clock-div = <2>;
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};
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lspclk: lspclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&pclk>;
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/* Fixed divider of 2 */
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clock-div = <2>;
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};
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hclkdiv1024: hclkdiv1024 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hclk>;
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/* Fixed divider of 1024 */
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clock-div = <1024>;
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};
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traceclk: traceclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sysclk>;
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/* Divider 1, 2, 3 or 4 */
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clock-div = <1>;
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};
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em01grpaclk: em01grpaclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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em01grpcclk: em01grpcclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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iadcclk: iadcclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&em01grpaclk>;
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};
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em23grpaclk: em23grpaclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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em4grpaclk: em4grpaclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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sysrtcclk: sysrtcclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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wdog0clk: wdog0clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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wdog1clk: wdog1clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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pcnt0clk: pcnt0clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&em23grpaclk>;
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};
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eusart0clk: eusart0clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&em01grpcclk>;
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};
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systickclk: systickclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hclk>;
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};
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vdac0clk: vdac0clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&em01grpaclk>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
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};
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power-states {
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/*
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* EM1 is a basic "CPU WFI idle", all high-freq clocks remain
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* enabled.
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*/
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pstate_em1: em1 {
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compatible = "zephyr,power-state";
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power-state-name = "runtime-idle";
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min-residency-us = <4>;
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/* HFXO remains active */
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exit-latency-us = <2>;
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};
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/*
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* EM2 is a deepsleep with HF clocks disabled by HW, voltages
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* scaled down, etc.
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*/
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pstate_em2: em2 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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min-residency-us = <260>;
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exit-latency-us = <250>;
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};
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/*
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* EM3 seems to be exactly the same as EM2 except that
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* LFXO & LFRCO should be disabled, so you must use ULFRCO
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* as BURTC clock for the system to not lose track of time and
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* wake up.
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*/
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pstate_em3: em3 {
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compatible = "zephyr,power-state";
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power-state-name = "standby";
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min-residency-us = <20000>;
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exit-latency-us = <2000>;
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};
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};
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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};
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soc {
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cmu: clock@50008000 {
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compatible = "silabs,series-clock";
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reg = <0x50008000 0x4000>;
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interrupts = <47 0>;
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interrupt-names = "cmu";
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status = "okay";
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#clock-cells = <2>;
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};
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fsrco: fsrco@50018000 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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reg = <0x50018000 0x4000>;
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clock-frequency = <DT_FREQ_M(20)>;
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};
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clk_hfxo: hfxo: hfxo@5a004000 {
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#clock-cells = <0>;
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compatible = "silabs,hfxo";
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reg = <0x5a004000 0x4000>;
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interrupts = <44 0>;
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interrupt-names = "hfxo";
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clock-frequency = <DT_FREQ_M(39)>;
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ctune = <140>;
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precision = <50>;
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status = "disabled";
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};
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lfxo: lfxo@50020000 {
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#clock-cells = <0>;
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compatible = "silabs,series2-lfxo";
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reg = <0x50020000 0x4000>;
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clock-frequency = <32768>;
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ctune = <63>;
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precision = <50>;
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timeout = <4096>;
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status = "disabled";
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};
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hfrcodpll: hfrcodpll@50010000 {
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#clock-cells = <0>;
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compatible = "silabs,series2-hfrcodpll";
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reg = <0x50010000 0x4000>;
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clock-frequency = <DT_FREQ_M(19)>;
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};
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hfrcoem23: hfrcoem23@5a000000 {
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#clock-cells = <0>;
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compatible = "silabs,series2-hfrcoem23";
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reg = <0x5a000000 0x4000>;
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clock-frequency = <DT_FREQ_M(19)>;
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};
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lfrco: lfrco@50024000 {
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#clock-cells = <0>;
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compatible = "silabs,series2-lfrco";
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reg = <0x50024000 0x4000>;
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clock-frequency = <32768>;
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};
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ulfrco: ulfrco@50028000 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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reg = <0x50028000 0x4000>;
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clock-frequency = <1000>;
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};
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clkin0: clkin0@5003c46c {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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reg = <0x5003c46c 0x4>;
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clock-frequency = <DT_FREQ_M(38)>;
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};
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msc: flash-controller@50030000 {
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compatible = "silabs,gecko-flash-controller";
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reg = <0x50030000 0x3148>;
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interrupts = <50 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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write-block-size = <4>;
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erase-block-size = <8192>;
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};
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};
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usart0: usart@5005c000 {
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compatible = "silabs,gecko-usart";
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reg = <0x5005C000 0x306c>;
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interrupts = <9 0>, <10 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <0>;
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clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
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status = "disabled";
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};
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eusart0: eusart@5b010000 {
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compatible = "silabs,gecko-spi-eusart";
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reg = <0x5B010000 0x4000>;
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interrupts = <11 0>, <12 0>;
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interrupt-names = "rx", "tx";
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clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>;
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status = "disabled";
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};
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eusart1: eusart@500a0000 {
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compatible = "silabs,gecko-spi-eusart";
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reg = <0x500A0000 0x4000>;
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interrupts = <13 0>, <14 0>;
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interrupt-names = "rx", "tx";
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clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>;
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status = "disabled";
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};
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burtc0: burtc@50064000 {
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compatible = "silabs,gecko-burtc";
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reg = <0x50064000 0x3034>;
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interrupts = <17 0>;
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clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
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status = "disabled";
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};
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se: semailbox@5c021000 {
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compatible = "silabs,gecko-semailbox";
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reg = <0x5c021000 0x1000>;
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status = "disabled";
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interrupts = <64 3>, <65 3>, <66 3>;
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interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX";
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};
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i2c0: i2c@5b000000 {
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compatible = "silabs,gecko-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x5b000000 0x3044>;
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interrupts = <27 0>;
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clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
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status = "disabled";
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};
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sysrtc0: stimer0: sysrtc@500a8000 {
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compatible = "silabs,gecko-stimer";
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reg = <0x500a8000 0x3054>;
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interrupts = <67 0>, <68 0>;
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interrupt-names = "sysrtc_app", "sysrtc_seq";
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clock-frequency = <32768>;
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prescaler = <1>;
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clocks = <&cmu CLOCK_SYSRTC0 CLOCK_BRANCH_SYSRTCCLK>;
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status = "disabled";
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};
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gpio: gpio@5003c000 {
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compatible = "silabs,gecko-gpio";
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reg = <0x5003c000 0x4000>;
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interrupts = <26 2>, <25 2>;
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interrupt-names = "GPIO_EVEN", "GPIO_ODD";
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clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@5003c030 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003c030 0x30>;
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peripheral-id = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiob: gpio@5003c060 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003c060 0x30>;
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peripheral-id = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpioc: gpio@5003c090 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003c090 0x30>;
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peripheral-id = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiod: gpio@5003c0C0 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003c0C0 0x30>;
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peripheral-id = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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};
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wdog0: wdog@5b004000 {
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compatible = "silabs,gecko-wdog";
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reg = <0x5b004000 0x2C>;
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peripheral-id = <0>;
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interrupts = <42 0>;
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clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
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status = "disabled";
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};
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wdog1: wdog@5b008000 {
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compatible = "silabs,gecko-wdog";
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reg = <0x5b008000 0x2C>;
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peripheral-id = <1>;
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interrupts = <43 0>;
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clocks = <&cmu CLOCK_WDOG1 CLOCK_BRANCH_WDOG1CLK>;
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status = "disabled";
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};
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adc0: adc@59004000 {
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compatible = "silabs,gecko-iadc";
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reg = <0x59004000 0x4000>;
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interrupts = <49 0>;
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clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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dcdc: dcdc@50094000 {
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compatible = "silabs,series2-dcdc";
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reg = <0x50094000 0x4000>;
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interrupts = <53 0>;
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status = "disabled";
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};
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};
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bt_hci_silabs: bt_hci_silabs {
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compatible = "silabs,bt-hci-efr32";
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status = "disabled";
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};
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};
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/ {
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pinctrl: pin-controller {
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/* Pin controller is a "virtual" device since SiLabs SoCs do pin
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* control in a distributed way (GPIO registers and PSEL
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* registers on each peripheral).
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*/
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compatible = "silabs,gecko-pinctrl";
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};
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hwinfo: hwinfo {
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compatible = "silabs,gecko-hwinfo";
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status = "disabled";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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