424 lines
9.2 KiB
Plaintext
424 lines
9.2 KiB
Plaintext
/* SPDX-License-Identifier: Apache-2.0 */
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#include <arm/armv7-m.dtsi>
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#include <mem.h>
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#include <freq.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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/ {
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clocks {
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uartclk: apb-pclk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(24)>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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cpu-power-states = <&idle &suspend_to_ram>;
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};
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power-states {
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idle: idle {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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/*
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* As Apollo4 datasheet, run_to_sleep and sleep_to_run
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* transition time are both lower than 1us, but
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* considering the software overhead we set a
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* bigger value.
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*/
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min-residency-us = <100>;
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exit-latency-us = <5>;
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};
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suspend_to_ram: suspend_to_ram {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-ram";
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/*
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* As Apollo4 datasheet, run_to_deepsleep transition
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* time is lower than 1us and deepsleep_to_run
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* transition time is about 25us, but considering
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* the software overhead, we set a bigger value.
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*/
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min-residency-us = <2000>;
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exit-latency-us = <125>;
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};
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};
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};
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/* TCM */
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tcm: tcm@10000000 {
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compatible = "zephyr,memory-region";
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reg = <0x10000000 0x10000>;
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zephyr,memory-region = "ITCM";
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};
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/* SRAM */
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sram0: memory@10010000 {
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compatible = "mmio-sram";
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reg = <0x10010000 0x2B0000>;
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};
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soc {
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compatible = "ambiq,apollo4p", "ambiq,apollo4x", "simple-bus";
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flash: flash-controller@18000 {
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compatible = "ambiq,flash-controller";
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reg = <0x00018000 0x1e8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* Flash region */
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flash0: flash@18000 {
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compatible = "soc-nv-flash";
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reg = <0x00018000 0x1e8000>;
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};
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};
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pwrcfg: pwrcfg@40021000 {
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compatible = "ambiq,pwrctrl";
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reg = <0x40021000 0x400>;
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#pwrcfg-cells = <2>;
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};
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stimer0: stimer@40008800 {
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compatible = "ambiq,stimer";
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reg = <0x40008800 0x80>;
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interrupts = <32 0>;
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status = "okay";
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};
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counter0: counter@40008200 {
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compatible = "ambiq,counter";
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reg = <0x40008200 0x20>;
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interrupts = <67 0>;
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clock-frequency = <DT_FREQ_M(6)>;
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clk-source = <1>;
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status = "disabled";
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};
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uart0: uart@4001c000 {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <0x4001c000 0x1000>;
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interrupts = <15 0>;
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interrupt-names = "UART0";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
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};
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uart1: uart@4001d000 {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <0x4001d000 0x1000>;
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interrupts = <16 0>;
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interrupt-names = "UART1";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
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};
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uart2: uart@4001e000 {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <0x4001e000 0x1000>;
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interrupts = <17 0>;
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interrupt-names = "UART2";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
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};
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uart3: uart@4001f000 {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <0x4001f000 0x1000>;
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interrupts = <18 0>;
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interrupt-names = "UART3";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
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};
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iom0_spi: spi@40050000 {
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reg = <0x40050000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <6 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
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};
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iom0_i2c: i2c@40050000 {
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reg = <0x40050000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <6 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
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};
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iom1_spi: spi@40051000 {
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reg = <0x40051000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <7 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
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};
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iom1_i2c: i2c@40051000 {
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reg = <0x40051000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <7 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
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};
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iom2_spi: spi@40052000 {
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reg = <0x40052000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
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};
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iom2_i2c: i2c@40052000 {
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reg = <0x40052000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
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};
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iom3_spi: spi@40053000 {
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reg = <0x40053000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <9 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
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};
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iom3_i2c: i2c@40053000 {
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reg = <0x40053000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <9 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
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};
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iom4_spi: spi@40054000 {
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reg = <0x40054000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <10 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
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};
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iom4_i2c: i2c@40054000 {
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reg = <0x40054000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <10 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
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};
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iom5_spi: spi@40055000 {
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reg = <0x40055000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <11 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
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};
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iom5_i2c: i2c@40055000 {
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reg = <0x40055000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <11 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
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};
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iom6_spi: spi@40056000 {
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reg = <0x40056000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <12 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
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};
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iom6_i2c: i2c@40056000 {
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reg = <0x40056000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <12 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
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};
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iom7_spi: spi@40057000 {
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reg = <0x40057000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <13 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
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};
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iom7_i2c: i2c@40057000 {
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reg = <0x40057000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <13 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
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};
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adc0: adc@40038000 {
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reg = <0x40038000 0x400>;
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interrupts = <19 0>;
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interrupt-names = "ADC";
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channel-count = <10>;
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internal-vref-mv = <1190>;
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status = "disabled";
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#io-channel-cells = <1>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x2000>;
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};
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mspi0: spi@40060000 {
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compatible = "ambiq,mspi";
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reg = <0x40060000 0x400>;
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interrupts = <20 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
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};
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mspi1: spi@40061000 {
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compatible = "ambiq,mspi";
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reg = <0x40061000 0x400>;
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interrupts = <21 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
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};
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mspi2: spi@40062000 {
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compatible = "ambiq,mspi";
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reg = <0x40062000 0x400>;
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interrupts = <22 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
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};
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rtc0: rtc@40004800 {
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compatible = "ambiq,rtc";
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reg = <0x40004800 0x210>;
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interrupts = <2 0>;
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alarms-count = <1>;
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status = "disabled";
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};
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usb: usb@400b0000 {
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compatible = "ambiq,usb";
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reg = <0x400B0000 0x4100>;
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interrupts = <27 0>;
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num-bidir-endpoints = <6>;
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maximum-speed = "full-speed";
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x4 0x400000>;
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};
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pinctrl: pin-controller@40010000 {
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compatible = "ambiq,apollo4-pinctrl";
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reg = <0x40010000 0x800>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio: gpio@40010000 {
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compatible = "ambiq,gpio";
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gpio-map-mask = <0xffffffe0 0xffffffc0>;
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gpio-map-pass-thru = <0x1f 0x3f>;
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gpio-map = <
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0x00 0x0 &gpio0_31 0x0 0x0
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0x20 0x0 &gpio32_63 0x0 0x0
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0x40 0x0 &gpio64_95 0x0 0x0
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0x60 0x0 &gpio96_127 0x0 0x0
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>;
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reg = <0x40010000>;
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#gpio-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ranges;
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gpio0_31: gpio0_31@0 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0>;
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interrupts = <56 0>;
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status = "disabled";
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};
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gpio32_63: gpio32_63@80 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x80>;
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interrupts = <57 0>;
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status = "disabled";
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};
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gpio64_95: gpio64_95@100 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x100>;
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interrupts = <58 0>;
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status = "disabled";
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};
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gpio96_127: gpio96_127@180 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x180>;
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interrupts = <59 0>;
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status = "disabled";
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};
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};
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};
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wdt0: watchdog@40024000 {
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compatible = "ambiq,watchdog";
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reg = <0x40024000 0x400>;
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interrupts = <1 0>;
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clock-frequency = <16>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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