149 lines
3.9 KiB
Plaintext
149 lines
3.9 KiB
Plaintext
# Microchip XEC ESPI configuration options
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# Copyright (c) 2019 Intel Corporation
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# Copyright (c) 2021 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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config ESPI_XEC_V2
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bool "XEC Microchip ESPI V2 driver"
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depends on SOC_SERIES_MEC172X
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help
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Enable the Microchip XEC ESPI driver for MEC172x series.
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config ESPI_XEC_PERIPHERAL_ACPI_SHD_MEM_SIZE
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int "Host I/O peripheral port size for shared memory in MEC172X series"
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depends on ESPI_XEC_V2 || ESPI_PERIPHERAL_ACPI_SHM_REGION
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default 256
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help
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This is the port size used by the Host and EC to communicate over
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the shared memory region to return the ACPI response data.
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config ESPI_XEC_PERIPHERAL_HOST_CMD_PARAM_SIZE
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int "Host I/O peripheral port size for ec host command in MEC172X series"
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depends on ESPI_XEC_V2 || ESPI_PERIPHERAL_EC_HOST_CMD
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default 256
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help
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This is the port size used by the Host and EC to communicate over
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the shared memory region to return the host command parameter data.
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if ESPI_XEC_V2
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config ESPI_OOB_CHANNEL
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default y
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config ESPI_FLASH_CHANNEL
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default y
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config ESPI_PERIPHERAL_HOST_IO
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default y
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config ESPI_PERIPHERAL_HOST_IO_PVT
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default y
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config ESPI_PERIPHERAL_DEBUG_PORT_80
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default y
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config ESPI_PERIPHERAL_8042_KBC
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default y
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config ESPI_PERIPHERAL_UART
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default y
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config ESPI_PERIPHERAL_UART_SOC_MAPPING
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int "SoC port exposed as logical eSPI UART"
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default 1
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depends on ESPI_PERIPHERAL_UART
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help
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This tells the driver to which SoC UART to direct the UART traffic
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send over eSPI from host. MEC172x implements two UARTs.
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config ESPI_PERIPHERAL_XEC_MAILBOX
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bool "SoC Mailbox over eSPI"
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depends on ESPI_PERIPHERAL_CHANNEL
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help
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Enable a 32 byte mailbox interface accessible via Host I/O over the
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ESPI Peripheral Channel.
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config ESPI_PERIPHERAL_XEC_ACPI_EC2
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bool "SoC ACPI EC 2 over eSPI"
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depends on ESPI_PERIPHERAL_CHANNEL
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help
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Enable ACPI EC2 interface accessible via Host I/O over the
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ESPI Peripheral Channel.
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config ESPI_PERIPHERAL_XEC_ACPI_EC3
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bool "SoC ACPI EC 3 over eSPI"
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depends on ESPI_PERIPHERAL_CHANNEL
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help
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Enable ACPI EC3 interface accessible via Host I/O over the
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ESPI Peripheral Channel.
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config ESPI_PERIPHERAL_XEC_ACPI_EC4
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bool "SoC ACPI EC 4 over eSPI"
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depends on ESPI_PERIPHERAL_CHANNEL
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help
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Enable ACPI EC4 interface accessible via Host I/O over the
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ESPI Peripheral Channel.
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config ESPI_PERIPHERAL_XEC_ACPI_PM1
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bool "SoC ACPI PM1 over eSPI"
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depends on ESPI_PERIPHERAL_CHANNEL
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help
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Enable ACPI PM1 interface accessible via Host I/O over the
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ESPI Peripheral Channel.
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config ESPI_PERIPHERAL_XEC_EMI0
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bool "SoC EMI 0 over eSPI"
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depends on ESPI_PERIPHERAL_CHANNEL
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help
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Enable EMI 0 interface accessible via Host I/O over the
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ESPI Peripheral Channel.
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config ESPI_PERIPHERAL_XEC_EMI1
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bool "SoC EMI 1 over eSPI"
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depends on ESPI_PERIPHERAL_CHANNEL
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help
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Enable EMI 1 interface accessible via Host I/O over the
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ESPI Peripheral Channel.
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config ESPI_PERIPHERAL_XEC_EMI2
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bool "SoC EMI 2 over eSPI"
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depends on ESPI_PERIPHERAL_CHANNEL
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help
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Enable EMI 2 interface accessible via Host I/O over the
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ESPI Peripheral Channel.
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config ESPI_OOB_BUFFER_SIZE
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int "eSPI OOB channel buffer size in bytes"
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default 128
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depends on ESPI_OOB_CHANNEL
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help
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Use minimum RAM buffer size by default but allow applications to
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override the value.
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Maximum OOB payload is 73 bytes.
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config ESPI_FLASH_BUFFER_SIZE
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int "eSPI Flash channel buffer size in bytes"
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default 256
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depends on ESPI_FLASH_CHANNEL
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help
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Use maximum RAM buffer size defined by spec but allow applications
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to override if eSPI host doesn't support it.
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config ESPI_SAF
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bool "XEC Microchip ESPI SAF driver"
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depends on ESPI_FLASH_CHANNEL
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default n
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help
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Enable Slave Attached Flash eSPI driver. SAF depends upon ESPI XEC driver
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and flash channel.
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config ESPI_SAF_INIT_PRIORITY
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int "ESPI SAF driver initialization priority"
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depends on ESPI_SAF
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default 4
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help
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Driver initialization priority for eSPI SAF driver.
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endif #ESPI_XEC_V2
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