604 lines
18 KiB
C
604 lines
18 KiB
C
/*
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* Copyright (c) 2020 Mohamed ElShahawi.
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_rtc
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#define CPU_RESET_REASON RTC_SW_CPU_RESET
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#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET)
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#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx6
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#undef CPU_RESET_REASON
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#define CPU_RESET_REASON SW_CPU_RESET
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#include <zephyr/dt-bindings/clock/esp32_clock.h>
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#include "esp32/rom/rtc.h"
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#include "soc/dport_reg.h"
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#elif defined(CONFIG_SOC_ESP32S2)
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#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7
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#include <zephyr/dt-bindings/clock/esp32s2_clock.h>
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#include "esp32s2/rom/rtc.h"
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#include "soc/dport_reg.h"
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#elif defined(CONFIG_SOC_ESP32S3)
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#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7
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#include <zephyr/dt-bindings/clock/esp32s3_clock.h>
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#include "esp32s3/rom/rtc.h"
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#include "soc/dport_reg.h"
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#include "esp32s3/clk.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#define DT_CPU_COMPAT espressif_riscv
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#include <zephyr/dt-bindings/clock/esp32c3_clock.h>
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#include "esp32c3/rom/rtc.h"
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#include <soc/soc_caps.h>
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#include <soc/soc.h>
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#include <soc/rtc.h>
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#endif
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#include "esp_rom_sys.h"
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#include <soc/rtc.h>
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#include <soc/i2s_reg.h>
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#include <soc/apb_ctrl_reg.h>
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#include <soc/timer_group_reg.h>
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#include <hal/clk_gate_ll.h>
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#include <soc.h>
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#include <zephyr/drivers/clock_control.h>
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#include <driver/periph_ctrl.h>
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#include <hal/cpu_hal.h>
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struct esp32_clock_config {
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int clk_src_sel;
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uint32_t cpu_freq;
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uint32_t xtal_freq_sel;
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int xtal_div;
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};
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static uint8_t const xtal_freq[] = {
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#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) || defined(CONFIG_SOC_ESP32S3)
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[ESP32_CLK_XTAL_24M] = 24,
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[ESP32_CLK_XTAL_26M] = 26,
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[ESP32_CLK_XTAL_40M] = 40,
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[ESP32_CLK_XTAL_AUTO] = 0
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#elif defined(CONFIG_SOC_ESP32S2)
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[ESP32_CLK_XTAL_40M] = 40,
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#elif defined(CONFIG_SOC_ESP32C3)
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[ESP32_CLK_XTAL_32M] = 32,
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[ESP32_CLK_XTAL_40M] = 40,
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#endif
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};
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static int clock_control_esp32_on(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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periph_module_enable((periph_module_t)sys);
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return 0;
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}
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static int clock_control_esp32_off(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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periph_module_disable((periph_module_t)sys);
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return 0;
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}
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static int clock_control_esp32_async_on(const struct device *dev,
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clock_control_subsys_t sys,
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clock_control_cb_t cb,
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void *user_data)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(sys);
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ARG_UNUSED(cb);
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ARG_UNUSED(user_data);
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return -ENOTSUP;
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}
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static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys);
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uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys);
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if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) {
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return CLOCK_CONTROL_STATUS_ON;
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}
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return CLOCK_CONTROL_STATUS_OFF;
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}
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static int clock_control_esp32_get_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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ARG_UNUSED(sub_system);
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rtc_cpu_freq_config_t config;
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rtc_clk_cpu_freq_get_config(&config);
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*rate = config.freq_mhz;
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return 0;
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}
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#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET)
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static void esp32_clock_perip_init(void)
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{
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uint32_t common_perip_clk;
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uint32_t hwcrypto_perip_clk;
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uint32_t wifi_bt_sdio_clk;
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#if !CONFIG_SMP
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soc_reset_reason_t rst_reas[1];
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#else
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soc_reset_reason_t rst_reas[2];
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#endif
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rst_reas[0] = esp_rom_get_reset_reason(0);
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#if CONFIG_SMP
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rst_reas[1] = esp_rom_get_reset_reason(1);
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#endif
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/* For reason that only reset CPU, do not disable the clocks
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* that have been enabled before reset.
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*/
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if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW ||
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rst_reas[0] == RESET_REASON_CPU0_RTC_WDT)
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#if CONFIG_SMP
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|| (rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_SW ||
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rst_reas[1] == RESET_REASON_CPU1_RTC_WDT)
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#endif
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) {
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common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
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hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG);
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wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
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} else {
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common_perip_clk = DPORT_WDG_CLK_EN |
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DPORT_PCNT_CLK_EN |
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DPORT_LEDC_CLK_EN |
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DPORT_TIMERGROUP1_CLK_EN |
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DPORT_PWM0_CLK_EN |
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DPORT_TWAI_CLK_EN |
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DPORT_PWM1_CLK_EN |
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DPORT_PWM2_CLK_EN |
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DPORT_PWM3_CLK_EN;
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hwcrypto_perip_clk = DPORT_PERI_EN_AES |
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DPORT_PERI_EN_SHA |
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DPORT_PERI_EN_RSA |
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DPORT_PERI_EN_SECUREBOOT;
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wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
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DPORT_WIFI_CLK_BT_EN_M |
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DPORT_WIFI_CLK_UNUSED_BIT5 |
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DPORT_WIFI_CLK_UNUSED_BIT12 |
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DPORT_WIFI_CLK_SDIOSLAVE_EN |
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DPORT_WIFI_CLK_SDIO_HOST_EN |
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DPORT_WIFI_CLK_EMAC_EN;
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}
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/* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */
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common_perip_clk |= DPORT_I2S0_CLK_EN |
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DPORT_UART_CLK_EN |
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DPORT_SPI2_CLK_EN |
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DPORT_I2C_EXT0_CLK_EN |
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DPORT_UHCI0_CLK_EN |
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DPORT_RMT_CLK_EN |
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DPORT_UHCI1_CLK_EN |
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DPORT_SPI3_CLK_EN |
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DPORT_I2C_EXT1_CLK_EN |
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DPORT_I2S1_CLK_EN |
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DPORT_SPI_DMA_CLK_EN;
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common_perip_clk &= ~DPORT_SPI01_CLK_EN;
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common_perip_clk &= ~DPORT_SPI2_CLK_EN;
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common_perip_clk &= ~DPORT_SPI3_CLK_EN;
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/* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
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* the current is not reduced when disable I2S clock.
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*/
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DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(0), I2S_CLKA_ENA);
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DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(1), I2S_CLKA_ENA);
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/* Disable some peripheral clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
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/* Disable hardware crypto clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, hwcrypto_perip_clk);
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DPORT_SET_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, hwcrypto_perip_clk);
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/* Disable WiFi/BT/SDIO clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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}
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#endif
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#if defined(CONFIG_SOC_ESP32S2)
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static void esp32_clock_perip_init(void)
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{
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uint32_t common_perip_clk;
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uint32_t hwcrypto_perip_clk;
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uint32_t wifi_bt_sdio_clk;
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uint32_t common_perip_clk1;
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soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
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/* For reason that only reset CPU, do not disable the clocks
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* that have been enabled before reset.
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*/
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if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
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rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
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common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
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hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG);
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wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
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} else {
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common_perip_clk = DPORT_WDG_CLK_EN |
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DPORT_I2S0_CLK_EN |
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DPORT_UART1_CLK_EN |
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DPORT_SPI2_CLK_EN |
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DPORT_I2C_EXT0_CLK_EN |
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DPORT_UHCI0_CLK_EN |
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DPORT_RMT_CLK_EN |
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DPORT_PCNT_CLK_EN |
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DPORT_LEDC_CLK_EN |
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DPORT_TIMERGROUP1_CLK_EN |
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DPORT_SPI3_CLK_EN |
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DPORT_PWM0_CLK_EN |
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DPORT_TWAI_CLK_EN |
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DPORT_PWM1_CLK_EN |
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DPORT_I2S1_CLK_EN |
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DPORT_SPI2_DMA_CLK_EN |
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DPORT_SPI3_DMA_CLK_EN |
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DPORT_PWM2_CLK_EN |
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DPORT_PWM3_CLK_EN;
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common_perip_clk1 = 0;
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hwcrypto_perip_clk = DPORT_CRYPTO_AES_CLK_EN |
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DPORT_CRYPTO_SHA_CLK_EN |
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DPORT_CRYPTO_RSA_CLK_EN;
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wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
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DPORT_WIFI_CLK_BT_EN_M |
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DPORT_WIFI_CLK_UNUSED_BIT5 |
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DPORT_WIFI_CLK_UNUSED_BIT12 |
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DPORT_WIFI_CLK_SDIOSLAVE_EN |
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DPORT_WIFI_CLK_SDIO_HOST_EN |
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DPORT_WIFI_CLK_EMAC_EN;
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}
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/* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */
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common_perip_clk |= DPORT_I2S0_CLK_EN |
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DPORT_UART1_CLK_EN |
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DPORT_USB_CLK_EN |
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DPORT_SPI2_CLK_EN |
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DPORT_I2C_EXT0_CLK_EN |
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DPORT_UHCI0_CLK_EN |
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DPORT_RMT_CLK_EN |
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DPORT_UHCI1_CLK_EN |
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DPORT_SPI3_CLK_EN |
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DPORT_I2C_EXT1_CLK_EN |
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DPORT_I2S1_CLK_EN |
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DPORT_SPI2_DMA_CLK_EN |
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DPORT_SPI3_DMA_CLK_EN;
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common_perip_clk1 = 0;
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/* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
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* the current is not reduced when disable I2S clock.
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*/
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REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
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REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
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/* Disable some peripheral clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, common_perip_clk1);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, common_perip_clk1);
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/* Disable hardware crypto clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
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/* Disable WiFi/BT/SDIO clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
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/* Enable WiFi MAC and POWER clocks */
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DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN);
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/* Set WiFi light sleep clock source to RTC slow clock */
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DPORT_REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 0);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
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DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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}
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#endif
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#if defined(CONFIG_SOC_ESP32S3)
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static void esp32_clock_perip_init(void)
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{
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uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
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uint32_t common_perip_clk1 = 0;
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soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
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/* For reason that only reset CPU, do not disable the clocks
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* that have been enabled before reset.
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*/
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if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
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rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
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common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
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hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
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wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
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} else {
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common_perip_clk = SYSTEM_WDG_CLK_EN |
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SYSTEM_I2S0_CLK_EN |
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SYSTEM_UART1_CLK_EN |
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SYSTEM_UART2_CLK_EN |
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SYSTEM_USB_CLK_EN |
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SYSTEM_SPI2_CLK_EN |
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SYSTEM_I2C_EXT0_CLK_EN |
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SYSTEM_UHCI0_CLK_EN |
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SYSTEM_RMT_CLK_EN |
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SYSTEM_PCNT_CLK_EN |
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SYSTEM_LEDC_CLK_EN |
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SYSTEM_TIMERGROUP1_CLK_EN |
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SYSTEM_SPI3_CLK_EN |
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SYSTEM_SPI4_CLK_EN |
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SYSTEM_PWM0_CLK_EN |
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SYSTEM_TWAI_CLK_EN |
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SYSTEM_PWM1_CLK_EN |
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SYSTEM_I2S1_CLK_EN |
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SYSTEM_SPI2_DMA_CLK_EN |
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SYSTEM_SPI3_DMA_CLK_EN |
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SYSTEM_PWM2_CLK_EN |
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SYSTEM_PWM3_CLK_EN;
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common_perip_clk1 = 0;
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hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
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SYSTEM_CRYPTO_SHA_CLK_EN |
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SYSTEM_CRYPTO_RSA_CLK_EN;
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wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
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SYSTEM_WIFI_CLK_BT_EN_M |
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SYSTEM_WIFI_CLK_UNUSED_BIT5 |
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SYSTEM_WIFI_CLK_UNUSED_BIT12 |
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SYSTEM_WIFI_CLK_SDIO_HOST_EN;
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}
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/* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */
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common_perip_clk |= SYSTEM_I2S0_CLK_EN |
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SYSTEM_UART1_CLK_EN |
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SYSTEM_UART2_CLK_EN |
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SYSTEM_USB_CLK_EN |
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SYSTEM_SPI2_CLK_EN |
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SYSTEM_I2C_EXT0_CLK_EN |
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SYSTEM_UHCI0_CLK_EN |
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SYSTEM_RMT_CLK_EN |
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SYSTEM_UHCI1_CLK_EN |
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SYSTEM_SPI3_CLK_EN |
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SYSTEM_SPI4_CLK_EN |
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SYSTEM_I2C_EXT1_CLK_EN |
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SYSTEM_I2S1_CLK_EN |
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SYSTEM_SPI2_DMA_CLK_EN |
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SYSTEM_SPI3_DMA_CLK_EN;
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common_perip_clk1 = 0;
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/* Disable some peripheral clocks. */
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CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
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CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
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/* Disable hardware crypto clocks. */
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CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
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/* Disable WiFi/BT/SDIO clocks. */
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CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
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|
SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
|
|
|
|
/* Set WiFi light sleep clock source to RTC slow clock */
|
|
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
|
|
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
|
|
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
|
|
|
|
/* Enable RNG clock. */
|
|
periph_module_enable(PERIPH_RNG_MODULE);
|
|
|
|
esp_rom_uart_tx_wait_idle(0);
|
|
esp_rom_uart_set_clock_baudrate(0, UART_CLK_FREQ_ROM, 115200);
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_SOC_ESP32C3)
|
|
static void esp32_clock_perip_init(void)
|
|
{
|
|
uint32_t common_perip_clk;
|
|
uint32_t hwcrypto_perip_clk;
|
|
uint32_t wifi_bt_sdio_clk;
|
|
uint32_t common_perip_clk1;
|
|
|
|
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
|
|
|
|
/* For reason that only reset CPU, do not disable the clocks
|
|
* that have been enabled before reset.
|
|
*/
|
|
if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
|
|
rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
|
|
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
|
|
hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
|
|
wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
|
|
} else {
|
|
common_perip_clk = SYSTEM_WDG_CLK_EN |
|
|
SYSTEM_I2S0_CLK_EN |
|
|
SYSTEM_UART1_CLK_EN |
|
|
SYSTEM_SPI2_CLK_EN |
|
|
SYSTEM_I2C_EXT0_CLK_EN |
|
|
SYSTEM_UHCI0_CLK_EN |
|
|
SYSTEM_RMT_CLK_EN |
|
|
SYSTEM_LEDC_CLK_EN |
|
|
SYSTEM_TIMERGROUP1_CLK_EN |
|
|
SYSTEM_SPI3_CLK_EN |
|
|
SYSTEM_SPI4_CLK_EN |
|
|
SYSTEM_TWAI_CLK_EN |
|
|
SYSTEM_I2S1_CLK_EN |
|
|
SYSTEM_SPI2_DMA_CLK_EN |
|
|
SYSTEM_SPI3_DMA_CLK_EN;
|
|
|
|
common_perip_clk1 = 0;
|
|
|
|
hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
|
|
SYSTEM_CRYPTO_SHA_CLK_EN |
|
|
SYSTEM_CRYPTO_RSA_CLK_EN;
|
|
|
|
wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
|
|
SYSTEM_WIFI_CLK_BT_EN_M |
|
|
SYSTEM_WIFI_CLK_UNUSED_BIT5 |
|
|
SYSTEM_WIFI_CLK_UNUSED_BIT12;
|
|
}
|
|
|
|
/* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */
|
|
common_perip_clk |= SYSTEM_I2S0_CLK_EN |
|
|
SYSTEM_UART1_CLK_EN |
|
|
SYSTEM_SPI2_CLK_EN |
|
|
SYSTEM_I2C_EXT0_CLK_EN |
|
|
SYSTEM_UHCI0_CLK_EN |
|
|
SYSTEM_RMT_CLK_EN |
|
|
SYSTEM_UHCI1_CLK_EN |
|
|
SYSTEM_SPI3_CLK_EN |
|
|
SYSTEM_SPI4_CLK_EN |
|
|
SYSTEM_I2C_EXT1_CLK_EN |
|
|
SYSTEM_I2S1_CLK_EN |
|
|
SYSTEM_SPI2_DMA_CLK_EN |
|
|
SYSTEM_SPI3_DMA_CLK_EN;
|
|
|
|
common_perip_clk1 = 0;
|
|
|
|
/* Disable some peripheral clocks. */
|
|
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
|
|
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
|
|
|
|
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
|
|
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
|
|
|
|
/* Disable hardware crypto clocks. */
|
|
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
|
|
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
|
|
|
|
/* Disable WiFi/BT/SDIO clocks. */
|
|
CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
|
|
SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
|
|
|
|
/* Set WiFi light sleep clock source to RTC slow clock */
|
|
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
|
|
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
|
|
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
|
|
|
|
/* Enable RNG clock. */
|
|
periph_module_enable(PERIPH_RNG_MODULE);
|
|
}
|
|
#endif
|
|
|
|
static int clock_control_esp32_init(const struct device *dev)
|
|
{
|
|
const struct esp32_clock_config *cfg = dev->config;
|
|
rtc_cpu_freq_config_t old_config;
|
|
rtc_cpu_freq_config_t new_config;
|
|
bool res;
|
|
|
|
/* reset default config to use dts config */
|
|
if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) {
|
|
rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
|
|
|
|
clk_cfg.xtal_freq = xtal_freq[cfg->xtal_freq_sel];
|
|
clk_cfg.cpu_freq_mhz = cfg->cpu_freq;
|
|
clk_cfg.slow_freq = rtc_clk_slow_freq_get();
|
|
clk_cfg.fast_freq = rtc_clk_fast_freq_get();
|
|
rtc_clk_init(clk_cfg);
|
|
}
|
|
|
|
rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
|
|
|
|
rtc_clk_cpu_freq_get_config(&old_config);
|
|
|
|
const uint32_t old_freq_mhz = old_config.freq_mhz;
|
|
const uint32_t new_freq_mhz = cfg->cpu_freq;
|
|
|
|
res = rtc_clk_cpu_freq_mhz_to_config(cfg->cpu_freq, &new_config);
|
|
if (!res) {
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
/* wait uart output to be cleared */
|
|
esp_rom_uart_tx_wait_idle(0);
|
|
|
|
if (cfg->xtal_div >= 0) {
|
|
new_config.div = cfg->xtal_div;
|
|
}
|
|
|
|
if (cfg->clk_src_sel >= 0) {
|
|
new_config.source = cfg->clk_src_sel;
|
|
}
|
|
|
|
/* set new configuration */
|
|
rtc_clk_cpu_freq_set_config(&new_config);
|
|
|
|
/* Re-calculate the ccount to make time calculation correct */
|
|
cpu_hal_set_cycle_count((uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz);
|
|
|
|
esp32_clock_perip_init();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct clock_control_driver_api clock_control_esp32_api = {
|
|
.on = clock_control_esp32_on,
|
|
.off = clock_control_esp32_off,
|
|
.async_on = clock_control_esp32_async_on,
|
|
.get_rate = clock_control_esp32_get_rate,
|
|
.get_status = clock_control_esp32_get_status,
|
|
};
|
|
|
|
#define ESP32_CLOCK_SOURCE \
|
|
COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source), \
|
|
(DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source)), (-1))
|
|
|
|
#define ESP32_CLOCK_XTAL_DIV \
|
|
COND_CODE_1(DT_NODE_HAS_PROP(0, xtal_div), \
|
|
(DT_INST_PROP(0, xtal_div)), (-1))
|
|
|
|
static const struct esp32_clock_config esp32_clock_config0 = {
|
|
.clk_src_sel = ESP32_CLOCK_SOURCE,
|
|
.cpu_freq = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency) / 1000000,
|
|
.xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
|
|
.xtal_div = ESP32_CLOCK_XTAL_DIV
|
|
};
|
|
|
|
DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
|
|
&clock_control_esp32_init,
|
|
NULL,
|
|
NULL,
|
|
&esp32_clock_config0,
|
|
PRE_KERNEL_1,
|
|
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
|
|
&clock_control_esp32_api);
|
|
|
|
#ifndef CONFIG_SOC_ESP32C3
|
|
BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) ==
|
|
DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency),
|
|
"SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq");
|
|
#endif
|