zephyr/soc/riscv32/openisa_rv32m1
Anas Nashif a2fd7d70ec cleanup: include/: move misc/util.h to sys/util.h
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
..
CMakeLists.txt
Kconfig
Kconfig.defconfig driver: flash: add flash driver for the RV32M1 SOC 2019-06-03 10:43:47 -05:00
Kconfig.soc driver: flash: add flash driver for the RV32M1 SOC 2019-06-03 10:43:47 -05:00
dts_fixup.h boards: riscv32: rv32m1_vega: enable MCUboot for ri5cy core 2019-06-03 10:43:47 -05:00
linker.ld boards: riscv32: rv32m1_vega: enable MCUboot for ri5cy core 2019-06-03 10:43:47 -05:00
soc.c cleanup: include/: move misc/util.h to sys/util.h 2019-06-27 22:55:49 -04:00
soc.h soc: riscv32: Move rv32m1 sram memory definitions to dts 2019-05-06 19:09:59 -04:00
soc_context.h arch: soc: riscv32: Separate soc offsets from soc context save 2019-05-06 14:52:17 -05:00
soc_irq.S arch: soc: riscv32: Separate soc offsets from soc context save 2019-05-06 14:52:17 -05:00
soc_offsets.h arch: soc: riscv32: Separate soc offsets from soc context save 2019-05-06 14:52:17 -05:00
soc_ri5cy.h
soc_zero_riscy.h
vector.S
wdog.S