338 lines
8.7 KiB
C
338 lines
8.7 KiB
C
/*
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* Copyright (c) 2021, ATL Electronics
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT gd_gd32_usart
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#include <errno.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/drivers/uart.h>
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#include <gd32_usart.h>
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#include <gd32_rcu.h>
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/* Unify GD32 HAL USART status register name to USART_STAT */
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#ifndef USART_STAT
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#define USART_STAT USART_STAT0
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#endif
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struct gd32_usart_config {
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uint32_t reg;
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uint32_t rcu_periph_clock;
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struct reset_dt_spec reset;
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const struct pinctrl_dev_config *pcfg;
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uint32_t parity;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_config_func_t irq_config_func;
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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struct gd32_usart_data {
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uint32_t baud_rate;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t user_cb;
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void *user_data;
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void usart_gd32_isr(const struct device *dev)
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{
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struct gd32_usart_data *const data = dev->data;
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if (data->user_cb) {
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data->user_cb(dev, data->user_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static int usart_gd32_init(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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struct gd32_usart_data *const data = dev->data;
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uint32_t word_length;
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uint32_t parity;
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int ret;
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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/**
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* In order to keep the transfer data size to 8 bits(1 byte),
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* append word length to 9BIT if parity bit enabled.
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*/
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switch (cfg->parity) {
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case UART_CFG_PARITY_NONE:
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parity = USART_PM_NONE;
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word_length = USART_WL_8BIT;
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break;
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case UART_CFG_PARITY_ODD:
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parity = USART_PM_ODD;
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word_length = USART_WL_9BIT;
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break;
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case UART_CFG_PARITY_EVEN:
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parity = USART_PM_EVEN;
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word_length = USART_WL_9BIT;
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break;
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default:
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return -ENOTSUP;
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}
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rcu_periph_clock_enable(cfg->rcu_periph_clock);
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(void)reset_line_toggle_dt(&cfg->reset);
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usart_baudrate_set(cfg->reg, data->baud_rate);
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usart_parity_config(cfg->reg, parity);
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usart_word_length_set(cfg->reg, word_length);
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/* Default to 1 stop bit */
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usart_stop_bit_set(cfg->reg, USART_STB_1BIT);
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usart_receive_config(cfg->reg, USART_RECEIVE_ENABLE);
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usart_transmit_config(cfg->reg, USART_TRANSMIT_ENABLE);
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usart_enable(cfg->reg);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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cfg->irq_config_func(dev);
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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return 0;
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}
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static int usart_gd32_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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uint32_t status;
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status = usart_flag_get(cfg->reg, USART_FLAG_RBNE);
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if (!status) {
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return -EPERM;
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}
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*c = usart_data_receive(cfg->reg);
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return 0;
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}
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static void usart_gd32_poll_out(const struct device *dev, unsigned char c)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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usart_data_transmit(cfg->reg, c);
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while (usart_flag_get(cfg->reg, USART_FLAG_TBE) == RESET) {
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;
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}
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}
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static int usart_gd32_err_check(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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uint32_t status = USART_STAT(cfg->reg);
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int errors = 0;
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if (status & USART_FLAG_ORERR) {
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usart_flag_clear(cfg->reg, USART_FLAG_ORERR);
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errors |= UART_ERROR_OVERRUN;
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}
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if (status & USART_FLAG_PERR) {
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usart_flag_clear(cfg->reg, USART_FLAG_PERR);
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errors |= UART_ERROR_PARITY;
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}
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if (status & USART_FLAG_FERR) {
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usart_flag_clear(cfg->reg, USART_FLAG_FERR);
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errors |= UART_ERROR_FRAMING;
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}
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usart_flag_clear(cfg->reg, USART_FLAG_NERR);
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return errors;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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int usart_gd32_fifo_fill(const struct device *dev, const uint8_t *tx_data,
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int len)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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uint8_t num_tx = 0U;
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while ((len - num_tx > 0) &&
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usart_flag_get(cfg->reg, USART_FLAG_TBE)) {
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usart_data_transmit(cfg->reg, tx_data[num_tx++]);
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}
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return num_tx;
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}
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int usart_gd32_fifo_read(const struct device *dev, uint8_t *rx_data,
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const int size)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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uint8_t num_rx = 0U;
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while ((size - num_rx > 0) &&
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usart_flag_get(cfg->reg, USART_FLAG_RBNE)) {
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rx_data[num_rx++] = usart_data_receive(cfg->reg);
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}
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return num_rx;
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}
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void usart_gd32_irq_tx_enable(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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usart_interrupt_enable(cfg->reg, USART_INT_TC);
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}
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void usart_gd32_irq_tx_disable(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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usart_interrupt_disable(cfg->reg, USART_INT_TC);
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}
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int usart_gd32_irq_tx_ready(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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return usart_flag_get(cfg->reg, USART_FLAG_TBE) &&
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usart_interrupt_flag_get(cfg->reg, USART_INT_FLAG_TC);
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}
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int usart_gd32_irq_tx_complete(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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return usart_flag_get(cfg->reg, USART_FLAG_TC);
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}
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void usart_gd32_irq_rx_enable(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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usart_interrupt_enable(cfg->reg, USART_INT_RBNE);
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}
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void usart_gd32_irq_rx_disable(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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usart_interrupt_disable(cfg->reg, USART_INT_RBNE);
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}
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int usart_gd32_irq_rx_ready(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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return usart_flag_get(cfg->reg, USART_FLAG_RBNE);
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}
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void usart_gd32_irq_err_enable(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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usart_interrupt_enable(cfg->reg, USART_INT_ERR);
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usart_interrupt_enable(cfg->reg, USART_INT_PERR);
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}
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void usart_gd32_irq_err_disable(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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usart_interrupt_disable(cfg->reg, USART_INT_ERR);
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usart_interrupt_disable(cfg->reg, USART_INT_PERR);
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}
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int usart_gd32_irq_is_pending(const struct device *dev)
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{
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const struct gd32_usart_config *const cfg = dev->config;
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return ((usart_flag_get(cfg->reg, USART_FLAG_RBNE) &&
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usart_interrupt_flag_get(cfg->reg, USART_INT_FLAG_RBNE)) ||
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(usart_flag_get(cfg->reg, USART_FLAG_TC) &&
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usart_interrupt_flag_get(cfg->reg, USART_INT_FLAG_TC)));
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}
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void usart_gd32_irq_callback_set(const struct device *dev,
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uart_irq_callback_user_data_t cb,
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void *user_data)
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{
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struct gd32_usart_data *const data = dev->data;
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data->user_cb = cb;
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data->user_data = user_data;
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static const struct uart_driver_api usart_gd32_driver_api = {
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.poll_in = usart_gd32_poll_in,
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.poll_out = usart_gd32_poll_out,
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.err_check = usart_gd32_err_check,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = usart_gd32_fifo_fill,
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.fifo_read = usart_gd32_fifo_read,
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.irq_tx_enable = usart_gd32_irq_tx_enable,
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.irq_tx_disable = usart_gd32_irq_tx_disable,
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.irq_tx_ready = usart_gd32_irq_tx_ready,
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.irq_tx_complete = usart_gd32_irq_tx_complete,
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.irq_rx_enable = usart_gd32_irq_rx_enable,
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.irq_rx_disable = usart_gd32_irq_rx_disable,
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.irq_rx_ready = usart_gd32_irq_rx_ready,
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.irq_err_enable = usart_gd32_irq_err_enable,
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.irq_err_disable = usart_gd32_irq_err_disable,
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.irq_is_pending = usart_gd32_irq_is_pending,
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.irq_callback_set = usart_gd32_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#define GD32_USART_IRQ_HANDLER(n) \
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static void usart_gd32_config_func_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), \
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DT_INST_IRQ(n, priority), \
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usart_gd32_isr, \
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DEVICE_DT_INST_GET(n), \
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0); \
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irq_enable(DT_INST_IRQN(n)); \
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}
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#define GD32_USART_IRQ_HANDLER_FUNC_INIT(n) \
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.irq_config_func = usart_gd32_config_func_##n
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#else /* CONFIG_UART_INTERRUPT_DRIVEN */
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#define GD32_USART_IRQ_HANDLER(n)
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#define GD32_USART_IRQ_HANDLER_FUNC_INIT(n)
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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#define GD32_USART_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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GD32_USART_IRQ_HANDLER(n) \
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static struct gd32_usart_data usart_gd32_data_##n = { \
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.baud_rate = DT_INST_PROP(n, current_speed), \
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}; \
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static const struct gd32_usart_config usart_gd32_config_##n = { \
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.reg = DT_INST_REG_ADDR(n), \
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.rcu_periph_clock = DT_INST_PROP(n, rcu_periph_clock), \
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.reset = RESET_DT_SPEC_INST_GET(n), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE), \
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GD32_USART_IRQ_HANDLER_FUNC_INIT(n) \
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}; \
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DEVICE_DT_INST_DEFINE(n, &usart_gd32_init, \
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NULL, \
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&usart_gd32_data_##n, \
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&usart_gd32_config_##n, PRE_KERNEL_1, \
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CONFIG_SERIAL_INIT_PRIORITY, \
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&usart_gd32_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(GD32_USART_INIT)
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