316 lines
9.2 KiB
C
316 lines
9.2 KiB
C
/* spi_dw.h - Designware SPI driver private definitions */
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/*
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* Copyright (c) 2015 Intel Corporation.
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* Copyright (c) 2023 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_SPI_SPI_DW_H_
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#define ZEPHYR_DRIVERS_SPI_SPI_DW_H_
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#include <string.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/spi.h>
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#include "spi_context.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef void (*spi_dw_config_t)(void);
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typedef uint32_t (*spi_dw_read_t)(uint8_t size, mm_reg_t addr, uint32_t off);
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typedef void (*spi_dw_write_t)(uint8_t size, uint32_t data, mm_reg_t addr, uint32_t off);
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typedef void (*spi_dw_set_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
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typedef void (*spi_dw_clear_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
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typedef int (*spi_dw_test_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
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/* Private structures */
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struct spi_dw_config {
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DEVICE_MMIO_ROM;
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uint32_t clock_frequency;
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spi_dw_config_t config_func;
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bool serial_target;
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uint8_t fifo_depth;
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uint8_t max_xfer_size;
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#ifdef CONFIG_PINCTRL
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const struct pinctrl_dev_config *pcfg;
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#endif
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spi_dw_read_t read_func;
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spi_dw_write_t write_func;
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spi_dw_set_bit_t set_bit_func;
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spi_dw_clear_bit_t clear_bit_func;
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spi_dw_test_bit_t test_bit_func;
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};
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struct spi_dw_data {
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DEVICE_MMIO_RAM;
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struct spi_context ctx;
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uint8_t dfs; /* dfs in bytes: 1,2 or 4 */
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uint8_t fifo_diff; /* cannot be bigger than FIFO depth */
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};
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/* Register operation functions */
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#define DT_INST_NODE_PROP_NOT_OR(inst, prop) \
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!DT_INST_PROP(inst, prop) ||
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#define DT_ANY_INST_NOT_PROP_STATUS_OKAY(prop) \
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(DT_INST_FOREACH_STATUS_OKAY_VARGS(DT_INST_NODE_PROP_NOT_OR, prop) 0)
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#define DT_INST_NODE_PROP_AND_OR(inst, prop) \
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DT_INST_PROP(inst, prop) ||
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#define DT_ANY_INST_PROP_STATUS_OKAY(prop) \
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(DT_INST_FOREACH_STATUS_OKAY_VARGS(DT_INST_NODE_PROP_AND_OR, prop) 0)
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#if DT_ANY_INST_PROP_STATUS_OKAY(aux_reg)
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static uint32_t aux_reg_read(uint8_t size, mm_reg_t addr, uint32_t off)
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{
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ARG_UNUSED(size);
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return sys_in32(addr + off/4);
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}
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static void aux_reg_write(uint8_t size, uint32_t data, mm_reg_t addr, uint32_t off)
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{
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ARG_UNUSED(size);
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sys_out32(data, addr + off/4);
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}
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static void aux_reg_set_bit(uint8_t bit, mm_reg_t addr, uint32_t off)
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{
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sys_io_set_bit(addr + off/4, bit);
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}
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static void aux_reg_clear_bit(uint8_t bit, mm_reg_t addr, uint32_t off)
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{
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sys_io_clear_bit(addr + off/4, bit);
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}
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static int aux_reg_test_bit(uint8_t bit, mm_reg_t addr, uint32_t off)
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{
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return sys_io_test_bit(addr + off/4, bit);
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}
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#endif
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#if DT_ANY_INST_NOT_PROP_STATUS_OKAY(aux_reg)
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static uint32_t reg_read(uint8_t size, mm_reg_t addr, uint32_t off)
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{
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switch (size) {
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case 8:
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return sys_read8(addr + off);
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case 16:
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return sys_read16(addr + off);
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case 32:
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return sys_read32(addr + off);
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default:
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return -EINVAL;
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}
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}
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static void reg_write(uint8_t size, uint32_t data, mm_reg_t addr, uint32_t off)
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{
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switch (size) {
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case 8:
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sys_write8(data, addr + off); break;
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case 16:
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sys_write16(data, addr + off); break;
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case 32:
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sys_write32(data, addr + off); break;
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default:
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break;
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}
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}
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static void reg_set_bit(uint8_t bit, mm_reg_t addr, uint32_t off)
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{
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sys_set_bit(addr + off, bit);
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}
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static void reg_clear_bit(uint8_t bit, mm_reg_t addr, uint32_t off)
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{
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sys_clear_bit(addr + off, bit);
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}
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static int reg_test_bit(uint8_t bit, mm_reg_t addr, uint32_t off)
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{
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return sys_test_bit(addr + off, bit);
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}
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#endif
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/* Helper macros */
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#define SPI_DW_CLK_DIVIDER(clock_freq, ssi_clk_hz) \
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((clock_freq / ssi_clk_hz) & 0xFFFF)
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#define DEFINE_MM_REG_READ(__reg, __off, __sz) \
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static inline uint32_t read_##__reg(const struct device *dev) \
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{ \
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const struct spi_dw_config *info = dev->config; \
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return info->read_func(__sz, (mm_reg_t)DEVICE_MMIO_GET(dev), __off); \
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}
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#define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \
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static inline void write_##__reg(const struct device *dev, uint32_t data)\
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{ \
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const struct spi_dw_config *info = dev->config; \
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info->write_func(__sz, data, (mm_reg_t)DEVICE_MMIO_GET(dev), __off); \
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}
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#define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline void set_bit_##__reg_bit(const struct device *dev) \
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{ \
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const struct spi_dw_config *info = dev->config; \
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info->set_bit_func(__bit, (mm_reg_t)DEVICE_MMIO_GET(dev), __reg_off); \
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}
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#define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline void clear_bit_##__reg_bit(const struct device *dev)\
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{ \
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const struct spi_dw_config *info = dev->config; \
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info->clear_bit_func(__bit, (mm_reg_t)DEVICE_MMIO_GET(dev), __reg_off); \
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}
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#define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \
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static inline int test_bit_##__reg_bit(const struct device *dev)\
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{ \
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const struct spi_dw_config *info = dev->config; \
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return info->test_bit_func(__bit, (mm_reg_t)DEVICE_MMIO_GET(dev), __reg_off); \
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}
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/* Common registers settings, bits etc... */
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/* CTRLR0 settings */
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#if !defined(CONFIG_SPI_DW_HSSI)
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#define DW_SPI_CTRLR0_SCPH_BIT (6)
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#define DW_SPI_CTRLR0_SCPOL_BIT (7)
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#define DW_SPI_CTRLR0_TMOD_SHIFT (8)
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#define DW_SPI_CTRLR0_SLV_OE_BIT (10)
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#define DW_SPI_CTRLR0_SRL_BIT (11)
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#else
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/* The register layout is different in the HSSI variant */
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#define DW_SPI_CTRLR0_SCPH_BIT (8)
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#define DW_SPI_CTRLR0_SCPOL_BIT (9)
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#define DW_SPI_CTRLR0_TMOD_SHIFT (10)
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#define DW_SPI_CTRLR0_SLV_OE_BIT (12)
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#define DW_SPI_CTRLR0_SRL_BIT (13)
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#endif
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#define DW_SPI_CTRLR0_SCPH BIT(DW_SPI_CTRLR0_SCPH_BIT)
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#define DW_SPI_CTRLR0_SCPOL BIT(DW_SPI_CTRLR0_SCPOL_BIT)
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#define DW_SPI_CTRLR0_SRL BIT(DW_SPI_CTRLR0_SRL_BIT)
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#define DW_SPI_CTRLR0_SLV_OE BIT(DW_SPI_CTRLR0_SLV_OE_BIT)
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#define DW_SPI_CTRLR0_TMOD_TX_RX (0)
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#define DW_SPI_CTRLR0_TMOD_TX (1 << DW_SPI_CTRLR0_TMOD_SHIFT)
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#define DW_SPI_CTRLR0_TMOD_RX (2 << DW_SPI_CTRLR0_TMOD_SHIFT)
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#define DW_SPI_CTRLR0_TMOD_EEPROM (3 << DW_SPI_CTRLR0_TMOD_SHIFT)
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#define DW_SPI_CTRLR0_TMOD_RESET (3 << DW_SPI_CTRLR0_TMOD_SHIFT)
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#define DW_SPI_CTRLR0_DFS_16(__bpw) ((__bpw) - 1)
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#define DW_SPI_CTRLR0_DFS_32(__bpw) (((__bpw) - 1) << 16)
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/* 0x38 represents the bits 8, 16 and 32. Knowing that 24 is bits 8 and 16
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* These are the bits were when you divide by 8, you keep the result as it is.
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* For all the other ones, 4 to 7, 9 to 15, etc... you need a +1,
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* since on such division it takes only the result above 0
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*/
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#define SPI_WS_TO_DFS(__bpw) (((__bpw) & ~0x38) ? \
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(((__bpw) / 8) + 1) : \
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((__bpw) / 8))
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/* SSIENR bits */
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#define DW_SPI_SSIENR_SSIEN_BIT (0)
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/* CLK_ENA bits */
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#define DW_SPI_CLK_ENA_BIT (0)
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/* SR bits and values */
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#define DW_SPI_SR_BUSY_BIT (0)
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#define DW_SPI_SR_TFNF_BIT (1)
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#define DW_SPI_SR_RFNE_BIT (3)
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/* IMR bits (ISR valid as well) */
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#define DW_SPI_IMR_TXEIM_BIT (0)
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#define DW_SPI_IMR_TXOIM_BIT (1)
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#define DW_SPI_IMR_RXUIM_BIT (2)
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#define DW_SPI_IMR_RXOIM_BIT (3)
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#define DW_SPI_IMR_RXFIM_BIT (4)
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#define DW_SPI_IMR_MSTIM_BIT (5)
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/* IMR values */
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#define DW_SPI_IMR_TXEIM BIT(DW_SPI_IMR_TXEIM_BIT)
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#define DW_SPI_IMR_TXOIM BIT(DW_SPI_IMR_TXOIM_BIT)
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#define DW_SPI_IMR_RXUIM BIT(DW_SPI_IMR_RXUIM_BIT)
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#define DW_SPI_IMR_RXOIM BIT(DW_SPI_IMR_RXOIM_BIT)
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#define DW_SPI_IMR_RXFIM BIT(DW_SPI_IMR_RXFIM_BIT)
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#define DW_SPI_IMR_MSTIM BIT(DW_SPI_IMR_MSTIM_BIT)
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/* ISR values (same as IMR) */
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#define DW_SPI_ISR_TXEIS DW_SPI_IMR_TXEIM
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#define DW_SPI_ISR_TXOIS DW_SPI_IMR_TXOIM
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#define DW_SPI_ISR_RXUIS DW_SPI_IMR_RXUIM
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#define DW_SPI_ISR_RXOIS DW_SPI_IMR_RXOIM
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#define DW_SPI_ISR_RXFIS DW_SPI_IMR_RXFIM
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#define DW_SPI_ISR_MSTIS DW_SPI_IMR_MSTIM
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/* Error interrupt */
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#define DW_SPI_ISR_ERRORS_MASK (DW_SPI_ISR_TXOIS | \
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DW_SPI_ISR_RXUIS | \
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DW_SPI_ISR_RXOIS | \
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DW_SPI_ISR_MSTIS)
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/* ICR Bit */
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#define DW_SPI_SR_ICR_BIT (0)
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/* Interrupt mask (IMR) */
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#define DW_SPI_IMR_MASK (0x0)
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#define DW_SPI_IMR_UNMASK (DW_SPI_IMR_TXEIM | \
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DW_SPI_IMR_TXOIM | \
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DW_SPI_IMR_RXUIM | \
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DW_SPI_IMR_RXOIM | \
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DW_SPI_IMR_RXFIM)
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#define DW_SPI_IMR_MASK_TX (~(DW_SPI_IMR_TXEIM | \
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DW_SPI_IMR_TXOIM))
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#define DW_SPI_IMR_MASK_RX (~(DW_SPI_IMR_RXUIM | \
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DW_SPI_IMR_RXOIM | \
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DW_SPI_IMR_RXFIM))
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/*
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* Including the right register definition file
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* SoC SPECIFIC!
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*
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* The file included next uses the DEFINE_MM_REG macros above to
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* declare functions. In this situation we'll leave the containing
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* extern "C" active in C++ compilations.
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*/
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#include "spi_dw_regs.h"
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#define z_extra_clock_on(...)
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#define z_extra_clock_off(...)
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/* Based on those macros above, here are common helpers for some registers */
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DEFINE_MM_REG_READ(txflr, DW_SPI_REG_TXFLR, 32)
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DEFINE_MM_REG_READ(rxflr, DW_SPI_REG_RXFLR, 32)
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#ifdef CONFIG_SPI_DW_ACCESS_WORD_ONLY
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DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 32)
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DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 32)
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DEFINE_MM_REG_READ(imr, DW_SPI_REG_IMR, 32)
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DEFINE_MM_REG_READ(isr, DW_SPI_REG_ISR, 32)
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#else
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DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 16)
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DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 8)
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DEFINE_MM_REG_READ(imr, DW_SPI_REG_IMR, 8)
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DEFINE_MM_REG_READ(isr, DW_SPI_REG_ISR, 8)
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#endif
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DEFINE_SET_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
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DEFINE_CLEAR_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
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DEFINE_TEST_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
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DEFINE_TEST_BIT_OP(sr_busy, DW_SPI_REG_SR, DW_SPI_SR_BUSY_BIT)
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_SPI_SPI_DW_H_ */
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