81 lines
1.9 KiB
C
81 lines
1.9 KiB
C
/*
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* Copyright (c) 2024 GARDENA GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT silabs_si32_apb
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#include <stdint.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/clock_control.h>
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#include <SI32_CLKCTRL_A_Type.h>
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#include <si32_device.h>
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struct clock_control_si32_apb_config {
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const struct device *clock_dev;
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uint32_t divider;
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};
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static int clock_control_si32_apb_on(const struct device *dev, clock_control_subsys_t sys)
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{
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return -ENOTSUP;
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}
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static int clock_control_si32_apb_off(const struct device *dev, clock_control_subsys_t sys)
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{
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return -ENOTSUP;
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}
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static int clock_control_si32_apb_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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const struct clock_control_si32_apb_config *config = dev->config;
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const int ret = clock_control_get_rate(config->clock_dev, NULL, rate);
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if (ret) {
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return ret;
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}
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*rate /= config->divider;
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return 0;
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}
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static struct clock_control_driver_api clock_control_si32_apb_api = {
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.on = clock_control_si32_apb_on,
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.off = clock_control_si32_apb_off,
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.get_rate = clock_control_si32_apb_get_rate,
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};
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static int clock_control_si32_apb_init(const struct device *dev)
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{
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const struct clock_control_si32_apb_config *config = dev->config;
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if (!device_is_ready(config->clock_dev)) {
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return -ENODEV;
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}
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if (config->divider == 1) {
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SI32_CLKCTRL_A_select_apb_divider_1(SI32_CLKCTRL_0);
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} else if (config->divider == 2) {
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SI32_CLKCTRL_A_select_apb_divider_2(SI32_CLKCTRL_0);
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} else {
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return -ENOTSUP;
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}
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return 0;
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}
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static const struct clock_control_si32_apb_config config = {
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
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.divider = DT_PROP(DT_NODELABEL(clk_apb), divider),
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};
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DEVICE_DT_INST_DEFINE(0, clock_control_si32_apb_init, NULL, NULL, &config, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_si32_apb_api);
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