84 lines
1.9 KiB
C
84 lines
1.9 KiB
C
/*
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* Copyright 2023 NXP
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*
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* Based on clock_control_mcux_scg.c, which is:
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* Copyright (c) 2019-2021 Vestas Wind Systems A/S
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_scg_k4
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/dt-bindings/clock/scg_k4.h>
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#include <soc.h>
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#include <fsl_clock.h>
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#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(clock_control_scg);
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#define MCUX_SCG_CLOCK_NODE(name) DT_INST_CHILD(0, name)
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static int mcux_scg_k4_on(const struct device *dev, clock_control_subsys_t sub_system)
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{
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return 0;
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}
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static int mcux_scg_k4_off(const struct device *dev, clock_control_subsys_t sub_system)
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{
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return 0;
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}
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static int mcux_scg_k4_get_rate(const struct device *dev, clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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clock_name_t clock_name;
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switch ((uint32_t)sub_system) {
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case SCG_K4_CORESYS_CLK:
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clock_name = kCLOCK_CoreSysClk;
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break;
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case SCG_K4_SLOW_CLK:
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clock_name = kCLOCK_SlowClk;
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break;
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case SCG_K4_PLAT_CLK:
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clock_name = kCLOCK_PlatClk;
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break;
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case SCG_K4_SYS_CLK:
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clock_name = kCLOCK_SysClk;
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break;
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case SCG_K4_BUS_CLK:
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clock_name = kCLOCK_BusClk;
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break;
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case SCG_K4_SYSOSC_CLK:
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clock_name = kCLOCK_ScgSysOscClk;
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break;
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case SCG_K4_SIRC_CLK:
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clock_name = kCLOCK_ScgSircClk;
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break;
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case SCG_K4_FIRC_CLK:
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clock_name = kCLOCK_ScgFircClk;
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break;
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case SCG_K4_RTCOSC_CLK:
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clock_name = kCLOCK_RtcOscClk;
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break;
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default:
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LOG_ERR("Unsupported clock name");
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return -EINVAL;
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}
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*rate = CLOCK_GetFreq(clock_name);
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return 0;
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}
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static const struct clock_control_driver_api mcux_scg_driver_api = {
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.on = mcux_scg_k4_on,
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.off = mcux_scg_k4_off,
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.get_rate = mcux_scg_k4_get_rate,
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};
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DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, NULL, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &mcux_scg_driver_api);
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