78 lines
1.6 KiB
Plaintext
78 lines
1.6 KiB
Plaintext
#
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# Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "RISCV32 configuration selection"
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depends on RISCV32
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source "arch/riscv32/soc/*/Kconfig.soc"
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endchoice
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menu "RISCV32 Options"
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depends on RISCV32
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config ARCH
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string
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default "riscv32"
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config ARCH_DEFCONFIG
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string
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default "arch/riscv32/defconfig"
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menu "RISCV32 Processor Options"
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config INCLUDE_RESET_VECTOR
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bool "Include Reset vector"
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default n
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help
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Include the reset vector stub that inits CPU and then jumps to __start
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config IRQ_OFFLOAD
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bool "Enable IRQ offload"
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default n
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help
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Enable irq_offload() API which allows functions to be synchronously
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run in interrupt context. Mainly useful for test cases.
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config RISCV_SOC_CONTEXT_SAVE
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bool "Enable SOC-based context saving in IRQ handler"
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default n
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help
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Enable SOC-based context saving, for SOCS which require saving of
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extra registers when entering an interrupt/exception
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config RISCV_SOC_INTERRUPT_INIT
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bool "Enable SOC-based interrupt initialization"
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default n
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help
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Enable SOC-based interrupt initialization
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(call soc_interrupt_init, within _IntLibInit when enabled)
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config RISCV_GENERIC_TOOLCHAIN
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bool "Compile using generic riscv32 toolchain"
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default y
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help
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Compile using generic riscv32 toolchain.
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Allow SOCs that have custom extended riscv ISA to still
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compile with generic riscv32 toolchain.
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config RISCV_HAS_CPU_IDLE
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bool "Does SOC has CPU IDLE instruction"
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default n
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help
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Does SOC has CPU IDLE instruction
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config GEN_ISR_TABLES
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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endmenu
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source "arch/riscv32/soc/*/Kconfig"
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endmenu
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