129 lines
4.1 KiB
Plaintext
129 lines
4.1 KiB
Plaintext
menu "x86 Core Options"
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depends on ARCH="x86"
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config NO_ISRS
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bool
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prompt "No Asynchronous Interrupts"
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default n
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help
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This option disables asynchronous interrupts support.
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menu "Memory Layout Options"
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config IDT_NUM_VECTORS
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int
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prompt "Number of IDT vectors"
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default 256
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help
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This option specifies the number of interrupt vector entries in the
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Interrupt Descriptor Table (IDT). By default all 256 vectors are
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supported in an IDT requiring 2048 bytes of memory.
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config NUM_GDT_SPARE_ENTRIES
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int
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prompt "Number of spare GDT entries"
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default 0
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help
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This option specifies the number of spare entries in the Global
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Descriptor Table (GDT).
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config PHYS_LOAD_ADDR
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hex "Physical load address"
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# Default value must be supplied by BSP
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help
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This option specifies the physical address where the kernel is loaded.
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endmenu
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menu "Board Capabilities"
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config BOI_HANDLER_SUPPORTED
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bool "BOI handler supported"
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default n
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help
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This option signifies that the target has one or more devices whose
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driver utilizes a "beginning of interrupt" handler that gets called
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before the standard interrupt handling code. This capability
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can be used by the driver to suppress spurious interrupts generated
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by the device (or for other purposes).
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config EOI_HANDLER_SUPPORTED
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bool "EOI handler supported"
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default n
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help
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This option signifies that the target has one or more devices whose
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driver utilizes an "end of interrupt" handler that gets called
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after the standard interrupt handling code. This capability
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can be used by the driver to tell the device that an interrupt
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has been handled (or for other purposes).
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config UNALIGNED_WRITE_UNSUPPORTED
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bool "Unaligned write Supported"
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default n
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help
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This option signifies that the target may not properly decode the
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IA-32 processor's byte enable (BE) lines, resulting in the inability
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to read/write unaligned quantities.
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config LOCK_INSTRUCTION_UNSUPPORTED
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bool "Lock Instruction Unsupported"
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default n
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help
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This option signifies that the target lacks support for the IA-32
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LOCK prefix instruction. Code running on such targets cannot
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use the LOCK prefix to perform read-modify-write operations in an
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atomic manner; such targets must utilize other techniques to perform
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atomic operations (such as locking interrupts).
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endmenu
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menu "Floating Point Options"
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depends on !CPU_FLOAT_UNSUPPORTED
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config FP_SHARING
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bool
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prompt "Floating point resource sharing" if !ENHANCED_SECURITY
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depends on FLOAT
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default n
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select AUTOMATIC_FP_ENABLING if ENHANCED_SECURITY
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help
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This option allows multiple tasks and fibers to safely utilize
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floating point hardware resources. Every task or fiber that wishes
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to use floating point instructions (i.e. x87 FPU, MMX, or SSEx) must
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be created with such support already enabled, or must enable this
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support via task_float_enable() or fiber_float_enable() before
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executing these instructions.
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Enabling this option adds 108 bytes to the stack size requirement
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of each task or fiber that utilizes x87 FPU or MMX instructions,
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and adds 464 bytes to the stack size requirement of each task or
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fiber that utilizes SSEx instructions. (The stack size requirement
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of tasks and fibers that do not utilize floating point instructions
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remains unchanged.)
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Disabling this option means that only a single task or fiber may
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utilize x87 FPU, MMX, or SSEx instructions. (The stack size
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requirement of all tasks and fibers remains unchanged.)
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config AUTOMATIC_FP_ENABLING
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bool
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prompt "Automatically enable floating point resource sharing" \
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if !ENHANCED_SECURITY
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depends on FP_SHARING
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default n
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help
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This option allows tasks and fibers to safely utilize floating
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point hardware resources without requiring them to first indicate
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their intention to do so. The system automatically detects when
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a task or fiber that does not currently have floating point support
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enabled uses a floating point instruction, and automatically executes
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task_float_enable() or fiber_float_enable() on its behalf. The
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task or fiber is enabled for using x87 FPU, MMX, or SSEx instructions
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if SSE is configured, otherwise it is enabled for using x87 FPU or
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MMX instructions only.
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endmenu
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endmenu
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