164 lines
3.6 KiB
Plaintext
164 lines
3.6 KiB
Plaintext
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (C) 2023, Intel Corporation
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*
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*/
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#include <arm64/armv8-a.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/dt-bindings/reset/intel_socfpga_reset.h>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells= <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x0>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x100>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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enable-method = "psci";
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reg = <0x200>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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enable-method = "psci";
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reg = <0x300>;
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};
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};
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gic: interrupt-controller@1d000000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x1d000000 0x10000>, /* GICD */
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<0x1d060000 0x80000>; /* GICR */
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <1>;
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its: msi-controller@1d040000 {
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compatible = "arm,gic-v3-its";
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reg = <0x1d040000 0x20000>;
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status = "disabled";
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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};
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sysmgr: sysmgr@10d12000 {
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compatible = "syscon";
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reg = <0x10d12000 0x1000>;
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};
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clock: clock@10d10000 {
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compatible = "intel,agilex5-clock";
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reg = <0x10d10000 0x1000>;
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#clock-cells = <1>;
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};
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psci {
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compatible = "arm,psci-1.1";
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method = "smc";
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};
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/* This is for setting the MMU region for pinmux */
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pinmux: pinmux@10d13000 {
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compatible = "syscon";
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reg = <0x10d13000 0x1000>;
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};
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mem0: memory@80100000 {
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device_type = "memory";
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reg = <0x80100000 DT_SIZE_M(8)>;
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};
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uart0: uart@10c02000 {
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compatible = "ns16550";
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reg-shift = <2>;
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reg = <0x10c02000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clock-frequency = <100000000>;
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resets = <&reset RSTMGR_UART0_RSTLINE>;
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status = "disabled";
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};
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reset: reset-controller@10D11000 {
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compatible = "intel,socfpga-reset";
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reg = <0x10D11000 0x100>;
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active-low;
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#reset-cells = <1>;
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status = "okay";
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};
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timer0: timer@10C03000 {
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compatible = "snps,dw-timers";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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reg = <0x10c03000 0x100>;
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clock-frequency = <100000000>;
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resets = <&reset RSTMGR_SPTIMER0_RSTLINE>;
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status = "disabled";
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};
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timer1: timer@10C03100 {
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compatible = "snps,dw-timers";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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reg = <0x10c03100 0x100>;
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clock-frequency = <100000000>;
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resets = <&reset RSTMGR_SPTIMER1_RSTLINE>;
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status = "disabled";
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};
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timer2: timer@10D00000 {
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compatible = "snps,dw-timers";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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reg = <0x10D00000 0x100>;
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clock-frequency = <100000000>;
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resets = <&reset RSTMGR_L4SYSTIMER0_RSTLINE>;
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status = "disabled";
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};
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timer3: timer@10D00100 {
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compatible = "snps,dw-timers";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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reg = <0x10D00100 0x100>;
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clock-frequency = <100000000>;
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resets = <&reset RSTMGR_L4SYSTIMER1_RSTLINE>;
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status = "disabled";
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};
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};
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