113 lines
3.2 KiB
YAML
113 lines
3.2 KiB
YAML
# Copyright (c) 2018, Google LLC.
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# Copyright (c) 2021, Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: Microchip XEC QMSPI controller with local DMA
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compatible: "microchip,xec-qmspi-ldma"
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include: [spi-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true
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girqs:
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type: array
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required: true
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description: |
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An array of integers encoding each interrupt signal connection.
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This information includes the aggregated GIRQ number, GIRQ bit
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position, aggregated GIRQ NVIC connection, and direct NVIC
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connection of the GIRQ bit.
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pcrs:
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type: array
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required: true
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description: |
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A two entry integer array containing the QMSPI PCR sleep register
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index and bit position.
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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lines:
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type: int
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required: false
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description: |
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QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
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MOSI and MISO or half-duplex on MOSI only. Lines set to 2
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or 4 indicate dual or quad I/O modes. Defaults to 1.
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port-sel:
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type: int
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required: false
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description: |
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SPI Port 0, 1, or 2. Port 0 is the shared SPI, port 1 is
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the private SPI, and port 2 is the internal SPI port for
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chip configurations with an embedded SPI flash. Defaults
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to port 0 (shared SPI port).
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chip-select:
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type: int
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required: false
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description: |
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Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
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Ports 1 and 2 implement CS0# only. Defaults to CS0#.
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dcsckon:
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type: int
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required: false
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description: |
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Delay in QMSPI main clocks from CS# assertion to first clock edge.
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If not present use hardware default value. Refer to chip documention
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for QMSPI input clock frequency.
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dckcsoff:
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type: int
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required: false
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description: |
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Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
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If not presetn use hardware default value. Refer to chip documention
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for QMSPI input clock frequency.
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dldh:
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type: int
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required: false
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description: |
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Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
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and WP#. If not present use hardware default value. Refer to chip
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documention for QMSPI input clock frequency.
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dcsda:
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type: int
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required: false
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description: |
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Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
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If not present use hardware default value. Refer to chip documention
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for QMSPI input clock frequency.
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cs1-freq:
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type: int
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required: false
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description: |
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Allows different frequencies for CS#0 and CS1# devices. This applies
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to ports implementing CS1#.
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tctradj:
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type: int
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required: false
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description: |
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An optional signed 8-bit value for adjusting the QMSPI control signal
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timing tap.
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tsckadj:
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type: int
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required: false
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description: |
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An optional signed 8-bit value for adjusting the QMSPI clock signal
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timing tap.
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