50 lines
2.4 KiB
YAML
50 lines
2.4 KiB
YAML
# Copyright (C) 2020 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: |
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GPIO pins exposed on Atmel Xplained Pro headers.
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The Xplained Pro layout provide a standard 20 pin header. A board can have
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one or more headers and can share pins. The extension headers are given
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names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
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to the embedded debugger. A header with ID7 signal from the embedded
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debugger connected should be called EXT7. PWR, EXT1, EXT2 and EXT3 are
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standard extension headers that have a predefined position according to the
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list below:
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* PWR is right angled at the top right hand side of the board. This
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header must always be implemented.
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* EXT1 is right angled at the top right hand side of the board, located
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below the PWR header. This header must always be present.
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* EXT2 is right angled and at the bottom right hand side of the board.
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This header is mandatory for medium and large boards and should not be
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implemented on small boards.
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* EXT3 is right angled pointing downwards
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All MCU boards have to implement at least PWR, EXT1, EXT2 (on medium and
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large boards), and EXT3. EXT4 to EXT7 can be placed differently depending
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on the board design. EXT4 to EXT7 can either be standard extension headers
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or application specific headers.
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Documentation:
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* https://www.microchip.com/development-tools/xplained-boards
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* http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Development-Kit_User%20Guide.pdf
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This binding provides a nexus mapping for 20 pins where pins are disposed
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to have a even and odd column:
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Connector
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Bind Pin Name Pin Pin Pin Name Bind
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ID 1 2 GND
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0 ADC(+) 3 4 ADC(-) 1
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2 UART(RTS)/GPIO1 5 6 UART(CTS)/GPIO2 3
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4 PWM(+) 7 8 PWM(-) 5
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6 IRQ/GPIO3 9 10 SPI(CS1)/GPIO4 7
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8 I2C(SDA) 11 12 I2C(SCL) 9
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10 UART(RX) 13 14 UART(TX) 11
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12 SPI(CS0) 15 16 SPI(MOSI) 13
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14 SPI(MISO) 17 18 SPI(SCK) 15
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GND 19 20 VDD(+3.3V)
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compatible: "atmel-xplained-pro-header"
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include: [gpio-nexus.yaml, base.yaml]
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