144 lines
3.6 KiB
C
144 lines
3.6 KiB
C
/**
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* Copyright (c) 2021 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ATOMIC_XTENSA_H_
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#define ZEPHYR_INCLUDE_ATOMIC_XTENSA_H_
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/* Included from <sys/atomic.h> */
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/* Recent GCC versions actually do have working atomics support on
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* Xtensa (and so should work with CONFIG_ATOMIC_OPERATIONS_BUILTIN),
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* but existing versions of Xtensa's XCC do not. So we define an
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* inline implementation here that is more or less identical
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*/
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static ALWAYS_INLINE atomic_val_t atomic_get(const atomic_t *target)
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{
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atomic_val_t ret;
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/* Actual Xtensa hardware seems to have only in-order
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* pipelines, but the architecture does define a barrier load,
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* so use it. There is a matching s32ri instruction, but
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* nothing in the Zephyr API requires a barrier store (all the
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* atomic write ops have exchange semantics.
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*/
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__asm__ volatile("l32ai %0, %1, 0"
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: "=r"(ret) : "r"(target) : "memory");
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return ret;
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}
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static ALWAYS_INLINE
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atomic_val_t xtensa_cas(atomic_t *addr, atomic_val_t oldval,
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atomic_val_t newval)
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{
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__asm__ volatile("wsr %1, SCOMPARE1; s32c1i %0, %2, 0"
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: "+r"(newval), "+r"(oldval) : "r"(addr) : "memory");
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return newval; /* got swapped with the old memory by s32c1i */
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}
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static ALWAYS_INLINE
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bool atomic_cas(atomic_t *target, atomic_val_t oldval, atomic_val_t newval)
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{
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return oldval == xtensa_cas(target, oldval, newval);
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}
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static ALWAYS_INLINE
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bool atomic_ptr_cas(atomic_ptr_t *target, void *oldval, void *newval)
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{
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return (atomic_val_t) oldval
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== xtensa_cas((atomic_t *) target, (atomic_val_t) oldval,
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(atomic_val_t) newval);
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}
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/* Generates an atomic exchange sequence that swaps the value at
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* address "target", whose old value is read to be "cur", with the
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* specified expression. Evaluates to the old value which was
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* atomically replaced.
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*/
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#define Z__GEN_ATOMXCHG(expr) ({ \
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atomic_val_t res, cur; \
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do { \
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cur = *target; \
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res = xtensa_cas(target, cur, (expr)); \
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} while (res != cur); \
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res; })
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static ALWAYS_INLINE
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atomic_val_t atomic_set(atomic_t *target, atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(value);
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}
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static ALWAYS_INLINE
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atomic_val_t atomic_add(atomic_t *target, atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(cur + value);
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}
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static ALWAYS_INLINE
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atomic_val_t atomic_sub(atomic_t *target, atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(cur - value);
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}
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static ALWAYS_INLINE
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atomic_val_t atomic_inc(atomic_t *target)
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{
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return Z__GEN_ATOMXCHG(cur + 1);
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}
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static ALWAYS_INLINE
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atomic_val_t atomic_dec(atomic_t *target)
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{
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return Z__GEN_ATOMXCHG(cur - 1);
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}
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static ALWAYS_INLINE atomic_val_t atomic_or(atomic_t *target,
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atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(cur | value);
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}
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static ALWAYS_INLINE atomic_val_t atomic_xor(atomic_t *target,
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atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(cur ^ value);
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}
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static ALWAYS_INLINE atomic_val_t atomic_and(atomic_t *target,
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atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(cur & value);
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}
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static ALWAYS_INLINE atomic_val_t atomic_nand(atomic_t *target,
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atomic_val_t value)
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{
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return Z__GEN_ATOMXCHG(~(cur & value));
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}
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static ALWAYS_INLINE void *atomic_ptr_get(const atomic_ptr_t *target)
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{
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return (void *) atomic_get((atomic_t *)target);
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}
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static ALWAYS_INLINE void *atomic_ptr_set(atomic_ptr_t *target, void *value)
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{
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return (void *) atomic_set((atomic_t *) target, (atomic_val_t) value);
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}
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static ALWAYS_INLINE atomic_val_t atomic_clear(atomic_t *target)
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{
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return atomic_set(target, 0);
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}
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static ALWAYS_INLINE void *atomic_ptr_clear(atomic_ptr_t *target)
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{
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return (void *) atomic_set((atomic_t *) target, 0);
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}
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#endif /* ZEPHYR_INCLUDE_ATOMIC_XTENSA_H_ */
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