zephyr/dts/arm/nuvoton/npcx9m7fb.dtsi

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/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include "npcx/npcx9.dtsi"
/ {
flash0: flash@10070000 {
reg = <0x10070000 DT_SIZE_K(256)>;
};
flash1: flash@64000000 {
reg = <0x64000000 DT_SIZE_K(512)>;
};
sram0: memory@200c0000 {
compatible = "mmio-sram";
reg = <0x200B0000 DT_SIZE_K(128)>;
};
soc-id {
device-id = <0x62>;
};
};
&qspi_fiu0 {
int_flash: w25q80@0 {
compatible ="nuvoton,npcx-fiu-nor";
size = <DT_SIZE_K(512 * 8)>;
reg = <0>;
status = "okay";
/* quad spi bus configuration of nor flash device */
qspi-flags = <NPCX_QSPI_SW_CS1>;
mapped-addr = <0x64000000>;
pinctrl-0 = <&int_flash_sl>;
pinctrl-names = "default";
};
};
/*
* Raising the interrupt priority of the MIWU group, which owns SHI CS, to the same as
* SHI's priority.
*/
&group_f1 {
irq-prio = <1>;
};