588 lines
16 KiB
C
588 lines
16 KiB
C
/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/drivers/dma.h>
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#include <errno.h>
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#include <zephyr/init.h>
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#include <string.h>
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#include <soc.h>
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#include <zephyr/sys/__assert.h>
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#include "dma_pl330.h"
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#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(dma_pl330);
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#define BYTE_WIDTH(burst_size) (1 << (burst_size))
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static int dma_pl330_submit(const struct device *dev, uint64_t dst,
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uint64_t src, uint32_t channel, uint32_t size);
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static void dma_pl330_get_counter(struct dma_pl330_ch_internal *ch_handle,
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uint32_t *psrc_byte_width,
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uint32_t *pdst_byte_width,
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uint32_t *ploop_counter,
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uint32_t *presidue)
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{
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uint32_t srcbytewidth, dstbytewidth;
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uint32_t loop_counter, residue;
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srcbytewidth = BYTE_WIDTH(ch_handle->src_burst_sz);
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dstbytewidth = BYTE_WIDTH(ch_handle->dst_burst_sz);
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loop_counter = ch_handle->trans_size /
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(srcbytewidth * (ch_handle->src_burst_len + 1));
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residue = ch_handle->trans_size - loop_counter *
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(srcbytewidth * (ch_handle->src_burst_len + 1));
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*psrc_byte_width = srcbytewidth;
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*pdst_byte_width = dstbytewidth;
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*ploop_counter = loop_counter;
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*presidue = residue;
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}
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static uint32_t dma_pl330_ch_ccr(struct dma_pl330_ch_internal *ch_handle)
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{
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uint32_t ccr;
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int secure = ch_handle->nonsec_mode ? SRC_PRI_NONSEC_VALUE :
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SRC_PRI_SEC_VALUE;
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ccr = ((ch_handle->dst_cache_ctrl & CC_SRCCCTRL_MASK) <<
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CC_DSTCCTRL_SHIFT) +
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((ch_handle->nonsec_mode) << CC_DSTNS_SHIFT) +
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(ch_handle->dst_burst_len << CC_DSTBRSTLEN_SHIFT) +
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(ch_handle->dst_burst_sz << CC_DSTBRSTSIZE_SHIFT) +
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(ch_handle->dst_inc << CC_DSTINC_SHIFT) +
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((ch_handle->src_cache_ctrl & CC_SRCCCTRL_MASK) <<
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CC_SRCCCTRL_SHIFT) +
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(secure << CC_SRCPRI_SHIFT) +
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(ch_handle->src_burst_len << CC_SRCBRSTLEN_SHIFT) +
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(ch_handle->src_burst_sz << CC_SRCBRSTSIZE_SHIFT) +
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(ch_handle->src_inc << CC_SRCINC_SHIFT);
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return ccr;
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}
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static void dma_pl330_calc_burstsz_len(struct dma_pl330_ch_internal *ch_handle,
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uint64_t dst, uint64_t src,
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uint32_t size)
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{
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uint32_t byte_width, burst_sz, burst_len;
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burst_sz = MAX_BURST_SIZE_LOG2;
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/* src, dst and size should be aligned to burst size in bytes */
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while ((src | dst | size) & ((BYTE_WIDTH(burst_sz)) - 1)) {
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burst_sz--;
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}
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byte_width = BYTE_WIDTH(burst_sz);
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burst_len = MAX_BURST_LEN;
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while (burst_len) {
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/* Choose burst length so that size is aligned */
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if (!(size % ((burst_len + 1) << byte_width))) {
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break;
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}
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burst_len--;
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}
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ch_handle->src_burst_len = burst_len;
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ch_handle->src_burst_sz = burst_sz;
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ch_handle->dst_burst_len = burst_len;
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ch_handle->dst_burst_sz = burst_sz;
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}
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#ifdef CONFIG_DMA_64BIT
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static void dma_pl330_cfg_dmac_add_control(uint32_t control_reg_base,
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uint64_t dst, uint64_t src, int ch)
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{
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uint32_t src_h = src >> 32;
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uint32_t dst_h = dst >> 32;
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uint32_t dmac_higher_addr;
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dmac_higher_addr = ((dst_h & HIGHER_32_ADDR_MASK) << DST_ADDR_SHIFT) |
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(src_h & HIGHER_32_ADDR_MASK);
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sys_write32(dmac_higher_addr,
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control_reg_base +
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(ch * CONTROL_OFFSET)
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);
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}
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#endif
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static void dma_pl330_config_channel(struct dma_pl330_ch_config *ch_cfg,
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uint64_t dst, uint64_t src, uint32_t size)
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{
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struct dma_pl330_ch_internal *ch_handle = &ch_cfg->internal;
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ch_handle->src_addr = src;
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ch_handle->dst_addr = dst;
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ch_handle->trans_size = size;
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if (ch_cfg->src_addr_adj == DMA_ADDR_ADJ_INCREMENT) {
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ch_handle->src_inc = 1;
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}
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if (ch_cfg->dst_addr_adj == DMA_ADDR_ADJ_INCREMENT) {
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ch_handle->dst_inc = 1;
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}
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}
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static inline uint32_t dma_pl330_gen_mov(mem_addr_t buf,
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enum dmamov_type type,
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uint32_t val)
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{
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sys_write8(OP_DMA_MOV, buf);
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sys_write8(type, buf + 1);
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sys_write8(val, buf + 2);
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sys_write8(val >> 8, buf + 3);
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sys_write8(val >> 16, buf + 4);
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sys_write8(val >> 24, buf + 5);
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return SZ_CMD_DMAMOV;
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}
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static inline void dma_pl330_gen_op(uint8_t opcode, uint32_t addr, uint32_t val)
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{
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sys_write8(opcode, addr);
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sys_write8(val, addr + 1);
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}
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static int dma_pl330_setup_ch(const struct device *dev,
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struct dma_pl330_ch_internal *ch_dat,
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int ch)
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{
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mem_addr_t dma_exec_addr;
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uint32_t offset = 0, ccr;
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uint32_t lp0_start, lp1_start;
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uint32_t loop_counter0 = 0, loop_counter1 = 0;
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uint32_t srcbytewidth, dstbytewidth;
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uint32_t loop_counter, residue;
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struct dma_pl330_dev_data *const dev_data = dev->data;
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struct dma_pl330_ch_config *channel_cfg;
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int secure = ch_dat->nonsec_mode ? SRC_PRI_NONSEC_VALUE :
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SRC_PRI_SEC_VALUE;
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channel_cfg = &dev_data->channels[ch];
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dma_exec_addr = channel_cfg->dma_exec_addr;
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offset += dma_pl330_gen_mov(dma_exec_addr,
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SAR, ch_dat->src_addr);
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offset += dma_pl330_gen_mov(dma_exec_addr + offset,
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DAR, ch_dat->dst_addr);
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ccr = dma_pl330_ch_ccr(ch_dat);
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offset += dma_pl330_gen_mov(dma_exec_addr + offset,
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CCR, ccr);
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dma_pl330_get_counter(ch_dat, &srcbytewidth, &dstbytewidth,
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&loop_counter, &residue);
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if (loop_counter >= PL330_LOOP_COUNTER0_MAX) {
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loop_counter0 = PL330_LOOP_COUNTER0_MAX - 1;
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loop_counter1 = loop_counter / PL330_LOOP_COUNTER0_MAX - 1;
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dma_pl330_gen_op(OP_DMA_LOOP_COUNT1, dma_exec_addr + offset,
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loop_counter1 & 0xff);
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offset = offset + 2;
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dma_pl330_gen_op(OP_DMA_LOOP, dma_exec_addr + offset,
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loop_counter0 & 0xff);
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offset = offset + 2;
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lp1_start = offset;
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lp0_start = offset;
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sys_write8(OP_DMA_LD, dma_exec_addr + offset);
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sys_write8(OP_DMA_ST, dma_exec_addr + offset + 1);
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offset = offset + 2;
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dma_pl330_gen_op(OP_DMA_LP_BK_JMP1, dma_exec_addr + offset,
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((offset - lp0_start) & 0xff));
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offset = offset + 2;
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dma_pl330_gen_op(OP_DMA_LOOP, dma_exec_addr + offset,
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(loop_counter0 & 0xff));
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offset = offset + 2;
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loop_counter1--;
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dma_pl330_gen_op(OP_DMA_LP_BK_JMP2, dma_exec_addr + offset,
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((offset - lp1_start) & 0xff));
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offset = offset + 2;
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}
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if ((loop_counter % PL330_LOOP_COUNTER0_MAX) != 0) {
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loop_counter0 = (loop_counter % PL330_LOOP_COUNTER0_MAX) - 1;
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dma_pl330_gen_op(OP_DMA_LOOP, dma_exec_addr + offset,
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(loop_counter0 & 0xff));
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offset = offset + 2;
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loop_counter1--;
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lp0_start = offset;
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sys_write8(OP_DMA_LD, dma_exec_addr + offset);
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sys_write8(OP_DMA_ST, dma_exec_addr + offset + 1);
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offset = offset + 2;
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dma_pl330_gen_op(OP_DMA_LP_BK_JMP1, dma_exec_addr + offset,
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((offset - lp0_start) & 0xff));
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offset = offset + 2;
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}
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if (residue != 0) {
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ccr = ((ch_dat->nonsec_mode) << CC_DSTNS_SHIFT) +
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(0x0 << CC_DSTBRSTLEN_SHIFT) +
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(0x0 << CC_DSTBRSTSIZE_SHIFT) +
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(ch_dat->dst_inc << CC_DSTINC_SHIFT) +
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(secure << CC_SRCPRI_SHIFT) +
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(0x0 << CC_SRCBRSTLEN_SHIFT) +
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(0x0 << CC_SRCBRSTSIZE_SHIFT) +
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ch_dat->src_inc;
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offset += dma_pl330_gen_mov(dma_exec_addr + offset,
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CCR, ccr);
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dma_pl330_gen_op(OP_DMA_LOOP, dma_exec_addr + offset,
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((residue - 1) & 0xff));
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offset = offset + 2;
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lp0_start = offset;
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sys_write8(OP_DMA_LD, dma_exec_addr + offset);
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sys_write8(OP_DMA_ST, dma_exec_addr + offset + 1);
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offset = offset + 2;
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dma_pl330_gen_op(OP_DMA_LP_BK_JMP1, dma_exec_addr + offset,
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((offset - lp0_start) & 0xff));
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offset = offset + 2;
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}
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sys_write8(OP_DMA_END, dma_exec_addr + offset);
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sys_write8(OP_DMA_END, dma_exec_addr + offset + 1);
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sys_write8(OP_DMA_END, dma_exec_addr + offset + 2);
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sys_write8(OP_DMA_END, dma_exec_addr + offset + 3);
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return 0;
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}
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static int dma_pl330_start_dma_ch(const struct device *dev,
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uint32_t reg_base, int ch, int secure)
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{
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struct dma_pl330_dev_data *const dev_data = dev->data;
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struct dma_pl330_ch_config *channel_cfg;
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uint32_t count = 0U;
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uint32_t data;
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channel_cfg = &dev_data->channels[ch];
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do {
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data = sys_read32(reg_base + DMAC_PL330_DBGSTATUS);
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if (++count > DMA_TIMEOUT_US) {
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return -ETIMEDOUT;
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}
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k_busy_wait(1);
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} while ((data & DATA_MASK) != 0);
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sys_write32(((ch << DMA_INTSR1_SHIFT) +
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(DMA_INTSR0 << DMA_INTSR0_SHIFT) +
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(secure << DMA_SECURE_SHIFT) + (ch << DMA_CH_SHIFT)),
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reg_base + DMAC_PL330_DBGINST0);
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sys_write32(channel_cfg->dma_exec_addr,
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reg_base + DMAC_PL330_DBGINST1);
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sys_write32(0x0, reg_base + DMAC_PL330_DBGCMD);
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count = 0U;
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do {
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data = sys_read32(reg_base + DMAC_PL330_DBGCMD);
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if (++count > DMA_TIMEOUT_US) {
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return -ETIMEDOUT;
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}
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k_busy_wait(1);
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} while ((data & DATA_MASK) != 0);
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return 0;
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}
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static int dma_pl330_wait(uint32_t reg_base, int ch)
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{
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int count = 0U;
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uint32_t cs0_reg = reg_base + DMAC_PL330_CS0;
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do {
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if (++count > DMA_TIMEOUT_US) {
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return -ETIMEDOUT;
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}
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k_busy_wait(1);
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} while (((sys_read32(cs0_reg + ch * 8)) & CH_STATUS_MASK) != 0);
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return 0;
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}
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static int dma_pl330_xfer(const struct device *dev, uint64_t dst,
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uint64_t src, uint32_t size, uint32_t channel,
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uint32_t *xfer_size)
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{
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struct dma_pl330_dev_data *const dev_data = dev->data;
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const struct dma_pl330_config *const dev_cfg = dev->config;
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struct dma_pl330_ch_config *channel_cfg;
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struct dma_pl330_ch_internal *ch_handle;
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int ret;
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uint32_t max_size;
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channel_cfg = &dev_data->channels[channel];
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ch_handle = &channel_cfg->internal;
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dma_pl330_calc_burstsz_len(ch_handle, dst, src, size);
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max_size = GET_MAX_DMA_SIZE((1 << ch_handle->src_burst_sz),
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ch_handle->src_burst_len);
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if (size > max_size) {
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size = max_size;
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}
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dma_pl330_config_channel(channel_cfg, dst, src, size);
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#ifdef CONFIG_DMA_64BIT
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/*
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* Pl330 supports only 4GB boundary, but boundary region can be
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* configured.
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* Support added for 36bit address, lower 32bit address are configured
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* in pl330 registers and higher 4bit address are configured in
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* LS_ICFG_DMAC_AXI_ADD_CONTROL registers.
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* Each channel has 1 control register to configure higher 4bit address.
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*/
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dma_pl330_cfg_dmac_add_control(dev_cfg->control_reg_base,
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dst, src, channel);
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#endif
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ret = dma_pl330_setup_ch(dev, ch_handle, channel);
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if (ret) {
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LOG_ERR("Failed to setup channel for DMA PL330");
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goto err;
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}
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ret = dma_pl330_start_dma_ch(dev, dev_cfg->reg_base, channel,
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ch_handle->nonsec_mode);
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if (ret) {
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LOG_ERR("Failed to start DMA PL330");
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goto err;
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}
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ret = dma_pl330_wait(dev_cfg->reg_base, channel);
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if (ret) {
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LOG_ERR("Failed waiting to finish DMA PL330");
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goto err;
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}
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*xfer_size = size;
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err:
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return ret;
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}
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#if CONFIG_DMA_64BIT
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static int dma_pl330_handle_boundary(const struct device *dev, uint64_t dst,
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uint64_t src, uint32_t channel,
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uint32_t size)
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{
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uint32_t dst_low = (uint32_t)dst;
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uint32_t src_low = (uint32_t)src;
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uint32_t transfer_size;
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int ret;
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/*
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* Pl330 has only 32bit registers and supports 4GB memory.
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* 4GB memory window can be configured using DMAC_AXI_ADD_CONTROL
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* registers.
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* Divide the DMA operation in 2 parts, 1st DMA from given address
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* to boundary (0xffffffff) and 2nd DMA on remaining size.
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*/
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if (size > (PL330_MAX_OFFSET - dst_low)) {
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transfer_size = PL330_MAX_OFFSET - dst_low;
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ret = dma_pl330_submit(dev, dst, src, channel,
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transfer_size);
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if (ret < 0) {
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return ret;
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}
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dst += transfer_size;
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src += transfer_size;
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size -= transfer_size;
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return dma_pl330_submit(dev, dst, src, channel, size);
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}
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if (size > (PL330_MAX_OFFSET - src_low)) {
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transfer_size = PL330_MAX_OFFSET - src_low;
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ret = dma_pl330_submit(dev, dst, src, channel, transfer_size);
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if (ret < 0) {
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return ret;
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}
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src += transfer_size;
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dst += transfer_size;
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size -= transfer_size;
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return dma_pl330_submit(dev, dst, src, channel, size);
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}
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return 0;
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}
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#endif
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static int dma_pl330_submit(const struct device *dev, uint64_t dst,
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uint64_t src,
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uint32_t channel, uint32_t size)
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{
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int ret;
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uint32_t xfer_size;
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#if CONFIG_DMA_64BIT
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/*
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* Pl330 has only 32bit registers and supports 4GB memory.
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* 4GB memory window can be configured using DMAC_AXI_ADD_CONTROL
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* registers. 32bit boundary (0xffffffff) should be check.
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* DMA on boundary condition is taken care in below function.
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*/
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if ((size > (PL330_MAX_OFFSET - (uint32_t)dst)) ||
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(size > (PL330_MAX_OFFSET - (uint32_t)src))) {
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return dma_pl330_handle_boundary(dev, dst, src,
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channel, size);
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}
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#endif
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while (size) {
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xfer_size = 0;
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ret = dma_pl330_xfer(dev, dst, src, size,
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channel, &xfer_size);
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if (ret) {
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return ret;
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}
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if (xfer_size > size) {
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return -EFAULT;
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}
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size -= xfer_size;
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dst += xfer_size;
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src += xfer_size;
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}
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return 0;
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}
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static int dma_pl330_configure(const struct device *dev, uint32_t channel,
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struct dma_config *cfg)
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{
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struct dma_pl330_dev_data *const dev_data = dev->data;
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struct dma_pl330_ch_config *channel_cfg;
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struct dma_pl330_ch_internal *ch_handle;
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if (channel >= MAX_DMA_CHANNELS) {
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return -EINVAL;
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}
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channel_cfg = &dev_data->channels[channel];
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k_mutex_lock(&channel_cfg->ch_mutex, K_FOREVER);
|
|
if (channel_cfg->channel_active) {
|
|
k_mutex_unlock(&channel_cfg->ch_mutex);
|
|
return -EBUSY;
|
|
}
|
|
channel_cfg->channel_active = 1;
|
|
k_mutex_unlock(&channel_cfg->ch_mutex);
|
|
|
|
if (cfg->channel_direction != MEMORY_TO_MEMORY) {
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
ch_handle = &channel_cfg->internal;
|
|
memset(ch_handle, 0, sizeof(*ch_handle));
|
|
|
|
channel_cfg->direction = cfg->channel_direction;
|
|
channel_cfg->dst_addr_adj = cfg->head_block->dest_addr_adj;
|
|
|
|
channel_cfg->src_addr = cfg->head_block->source_address;
|
|
channel_cfg->dst_addr = cfg->head_block->dest_address;
|
|
channel_cfg->trans_size = cfg->head_block->block_size;
|
|
|
|
channel_cfg->dma_callback = cfg->dma_callback;
|
|
channel_cfg->user_data = cfg->user_data;
|
|
|
|
if (cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_INCREMENT ||
|
|
cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_NO_CHANGE) {
|
|
channel_cfg->src_addr_adj = cfg->head_block->source_addr_adj;
|
|
} else {
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
if (cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_INCREMENT ||
|
|
cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_NO_CHANGE) {
|
|
channel_cfg->dst_addr_adj = cfg->head_block->dest_addr_adj;
|
|
} else {
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dma_pl330_transfer_start(const struct device *dev,
|
|
uint32_t channel)
|
|
{
|
|
struct dma_pl330_dev_data *const dev_data = dev->data;
|
|
struct dma_pl330_ch_config *channel_cfg;
|
|
int ret;
|
|
|
|
if (channel >= MAX_DMA_CHANNELS) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
channel_cfg = &dev_data->channels[channel];
|
|
ret = dma_pl330_submit(dev, channel_cfg->dst_addr,
|
|
channel_cfg->src_addr, channel,
|
|
channel_cfg->trans_size);
|
|
|
|
k_mutex_lock(&channel_cfg->ch_mutex, K_FOREVER);
|
|
channel_cfg->channel_active = 0;
|
|
k_mutex_unlock(&channel_cfg->ch_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dma_pl330_transfer_stop(const struct device *dev, uint32_t channel)
|
|
{
|
|
if (channel >= MAX_DMA_CHANNELS) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Nothing as of now */
|
|
return 0;
|
|
}
|
|
|
|
static int dma_pl330_initialize(const struct device *dev)
|
|
{
|
|
const struct dma_pl330_config *const dev_cfg = dev->config;
|
|
struct dma_pl330_dev_data *const dev_data = dev->data;
|
|
struct dma_pl330_ch_config *channel_cfg;
|
|
|
|
for (int channel = 0; channel < MAX_DMA_CHANNELS; channel++) {
|
|
channel_cfg = &dev_data->channels[channel];
|
|
channel_cfg->dma_exec_addr = dev_cfg->mcode_base +
|
|
(channel * MICROCODE_SIZE_MAX);
|
|
k_mutex_init(&channel_cfg->ch_mutex);
|
|
}
|
|
|
|
LOG_INF("Device %s initialized", dev->name);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dma_driver_api pl330_driver_api = {
|
|
.config = dma_pl330_configure,
|
|
.start = dma_pl330_transfer_start,
|
|
.stop = dma_pl330_transfer_stop,
|
|
};
|
|
|
|
static const struct dma_pl330_config pl330_config = {
|
|
.reg_base = DT_INST_REG_ADDR(0),
|
|
#ifdef CONFIG_DMA_64BIT
|
|
.control_reg_base = DT_INST_REG_ADDR_BY_NAME(0, control_regs),
|
|
#endif
|
|
.mcode_base = DT_INST_PROP_BY_IDX(0, microcode, 0),
|
|
};
|
|
|
|
static struct dma_pl330_dev_data pl330_data;
|
|
|
|
DEVICE_DT_INST_DEFINE(0, &dma_pl330_initialize, NULL,
|
|
&pl330_data, &pl330_config,
|
|
POST_KERNEL, CONFIG_DMA_INIT_PRIORITY,
|
|
&pl330_driver_api);
|