117 lines
3.0 KiB
C
117 lines
3.0 KiB
C
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <device.h>
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#include <system_timer.h>
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#include <board.h>
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typedef struct {
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uint32_t val_low;
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uint32_t val_high;
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uint32_t cmp_low;
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uint32_t cmp_high;
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} riscv_qemu_timer_t;
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static volatile riscv_qemu_timer_t *timer =
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(riscv_qemu_timer_t *)RISCV_QEMU_TIMER_BASE;
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static uint32_t accumulated_cycle_count;
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static uint64_t last_rtc_value;
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/*
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* riscv-qemu timer is a one shot timer that needs to be rearm upon
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* every interrupt. Timer clock is a 64-bits ART.
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* To arm timer, we need to read the RTC value and update the
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* timer compare register by the RTC value + time interval we want timer
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* to interrupt.
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*/
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static ALWAYS_INLINE void riscv_qemu_rearm_timer(void)
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{
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uint64_t rtc;
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/*
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* Following qemu implementation, the actual RTC read is performed
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* when reading low timer value register. Reading high timer value
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* just reads the most significant 32-bits of a cache value, obtained
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* from a previous read to the low timer value register.
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* Hence, always read timer->val_low first.
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*/
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rtc = timer->val_low;
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rtc |= ((uint64_t)timer->val_high << 32);
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last_rtc_value = rtc;
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/*
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* Rearm timer to generate an interrupt after
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* sys_clock_hw_cycles_per_tick
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*/
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rtc += sys_clock_hw_cycles_per_tick;
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timer->cmp_low = (uint32_t)(rtc & 0xffffffff);
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timer->cmp_high = (uint32_t)((rtc >> 32) & 0xffffffff);
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}
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static void riscv_qemu_timer_irq_handler(void *unused)
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{
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ARG_UNUSED(unused);
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accumulated_cycle_count += sys_clock_hw_cycles_per_tick;
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_sys_clock_tick_announce();
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/* Rearm timer */
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riscv_qemu_rearm_timer();
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}
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#ifdef CONFIG_TICKLESS_IDLE
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#error "Tickless idle not yet implemented for riscv32-qemu timer"
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#endif
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int _sys_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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IRQ_CONNECT(RISCV_QEMU_TIMER_IRQ, 0,
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riscv_qemu_timer_irq_handler, NULL, 0);
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irq_enable(RISCV_QEMU_TIMER_IRQ);
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/* Initialize timer, just call riscv_qemu_rearm_timer */
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riscv_qemu_rearm_timer();
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return 0;
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}
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/**
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*
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* @brief Read the platform's timer hardware
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*
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* This routine returns the current time in terms of timer hardware clock
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* cycles.
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*
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* @return up counter of elapsed clock cycles
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*/
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uint32_t k_cycle_get_32(void)
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{
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uint64_t rtc;
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rtc = timer->val_low;
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rtc |= ((uint64_t)timer->val_high << 32);
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/* rtc - last_rtc_value is always <= sys_clock_hw_cycles_per_tick */
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return accumulated_cycle_count + (uint32_t)(rtc - last_rtc_value);
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}
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