782 lines
20 KiB
C
782 lines
20 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @brief Driver for UART on ARM CMSDK APB UART.
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*
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* UART has two wires for RX and TX, and does not provide CTS or RTS.
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <clock_control/arm_clock_control.h>
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#include <misc/__assert.h>
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#include <board.h>
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#include <init.h>
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#include <uart.h>
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#include <sections.h>
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/* UART registers struct */
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struct uart_cmsdk_apb {
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/* offset: 0x000 (r/w) data register */
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volatile uint32_t data;
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/* offset: 0x004 (r/w) status register */
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volatile uint32_t state;
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/* offset: 0x008 (r/w) control register */
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volatile uint32_t ctrl;
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union {
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/* offset: 0x00c (r/ ) interrupt status register */
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volatile uint32_t intstatus;
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/* offset: 0x00c ( /w) interrupt clear register */
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volatile uint32_t intclear;
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};
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/* offset: 0x010 (r/w) baudrate divider register */
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volatile uint32_t bauddiv;
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};
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/* UART Bits */
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/* CTRL Register */
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#define UART_TX_EN (1 << 0)
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#define UART_RX_EN (1 << 1)
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#define UART_TX_IN_EN (1 << 2)
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#define UART_RX_IN_EN (1 << 3)
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#define UART_TX_OV_EN (1 << 4)
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#define UART_RX_OV_EN (1 << 5)
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#define UART_HS_TM_TX (1 << 6)
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/* STATE Register */
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#define UART_TX_BF (1 << 0)
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#define UART_RX_BF (1 << 1)
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#define UART_TX_B_OV (1 << 2)
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#define UART_RX_B_OV (1 << 3)
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/* INTSTATUS Register */
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#define UART_TX_IN (1 << 0)
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#define UART_RX_IN (1 << 1)
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#define UART_TX_OV_IN (1 << 2)
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#define UART_RX_OV_IN (1 << 3)
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/* Device data structure */
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struct uart_cmsdk_apb_dev_data {
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uint32_t baud_rate; /* Baud rate */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_t irq_cb;
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#endif
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/* UART Clock control in Active State */
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const struct arm_clock_control_t uart_cc_as;
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/* UART Clock control in Sleep State */
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const struct arm_clock_control_t uart_cc_ss;
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/* UART Clock control in Deep Sleep State */
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const struct arm_clock_control_t uart_cc_dss;
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};
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/* convenience defines */
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#define DEV_CFG(dev) \
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((const struct uart_device_config * const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct uart_cmsdk_apb_dev_data * const)(dev)->driver_data)
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#define UART_STRUCT(dev) \
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((volatile struct uart_cmsdk_apb *)(DEV_CFG(dev))->base)
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static const struct uart_driver_api uart_cmsdk_apb_driver_api;
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/**
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* @brief Set the baud rate
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*
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* This routine set the given baud rate for the UART.
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*
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* @param dev UART device struct
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*
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* @return N/A
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*/
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static void baudrate_set(struct device *dev)
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{
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volatile struct uart_cmsdk_apb *uart = UART_STRUCT(dev);
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const struct uart_device_config * const dev_cfg = DEV_CFG(dev);
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struct uart_cmsdk_apb_dev_data *const dev_data = DEV_DATA(dev);
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/*
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* If baudrate and/or sys_clk_freq are 0 the configuration remains
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* unchanged. It can be useful in case that Zephyr it is run via
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* a bootloader that brings up the serial and sets the baudrate.
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*/
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if ((dev_data->baud_rate != 0) && (dev_cfg->sys_clk_freq != 0)) {
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/* calculate baud rate divisor */
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uart->bauddiv = (dev_cfg->sys_clk_freq / dev_data->baud_rate);
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}
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}
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/**
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* @brief Initialize UART channel
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*
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* This routine is called to reset the chip in a quiescent state.
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* It is assumed that this function is called only once per UART.
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*
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* @param dev UART device struct
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*
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* @return 0
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*/
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static int uart_cmsdk_apb_init(struct device *dev)
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{
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volatile struct uart_cmsdk_apb *uart = UART_STRUCT(dev);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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const struct uart_device_config * const dev_cfg = DEV_CFG(dev);
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#endif
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#ifdef CONFIG_CLOCK_CONTROL
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/* Enable clock for subsystem */
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struct device *clk =
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device_get_binding(CONFIG_ARM_CLOCK_CONTROL_DEV_NAME);
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struct uart_cmsdk_apb_dev_data * const data = DEV_DATA(dev);
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#ifdef CONFIG_SOC_SERIES_BEETLE
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clock_control_on(clk, (clock_control_subsys_t *) &data->uart_cc_as);
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clock_control_on(clk, (clock_control_subsys_t *) &data->uart_cc_ss);
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clock_control_on(clk, (clock_control_subsys_t *) &data->uart_cc_dss);
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#endif /* CONFIG_SOC_SERIES_BEETLE */
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#endif /* CONFIG_CLOCK_CONTROL */
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/* Set baud rate */
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baudrate_set(dev);
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/* Enable receiver and transmitter */
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uart->ctrl = UART_RX_EN | UART_TX_EN;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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dev_cfg->irq_config_func(dev);
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#endif
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return 0;
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}
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/**
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* @brief Poll the device for input.
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*
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* @param dev UART device struct
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* @param c Pointer to character
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*
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* @return 0 if a character arrived, -1 if the input buffer if empty.
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*/
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static int uart_cmsdk_apb_poll_in(struct device *dev, unsigned char *c)
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{
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volatile struct uart_cmsdk_apb *uart = UART_STRUCT(dev);
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/* If the receiver is not ready returns -1 */
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if (!(uart->state & UART_RX_BF)) {
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return -1;
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}
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/* got a character */
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*c = (unsigned char)uart->data;
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return 0;
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}
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/**
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* @brief Output a character in polled mode.
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*
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* Checks if the transmitter is empty. If empty, a character is written to
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* the data register.
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*
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* @param dev UART device struct
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* @param c Character to send
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*
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* @return Sent character
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*/
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static unsigned char uart_cmsdk_apb_poll_out(struct device *dev,
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unsigned char c)
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{
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volatile struct uart_cmsdk_apb *uart = UART_STRUCT(dev);
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/* Wait for transmitter to be ready */
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while (uart->state & UART_TX_BF) {
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; /* Wait */
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}
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/* Send a character */
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uart->data = (uint32_t)c;
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return c;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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/**
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* @brief Fill FIFO with data
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*
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* @param dev UART device struct
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* @param tx_data Data to transmit
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* @param len Number of bytes to send
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*
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* @return the number of characters that have been read
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*/
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static int uart_cmsdk_apb_fifo_fill(struct device *dev,
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const uint8_t *tx_data, int len)
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{
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volatile struct uart_cmsdk_apb *uart = UART_STRUCT(dev);
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/* No hardware FIFO present */
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if (len && !(uart->state & UART_TX_BF)) {
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uart->data = *tx_data;
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return 1;
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}
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return 0;
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}
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/**
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* @brief Read data from FIFO
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*
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* @param dev UART device struct
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* @param rx_data Pointer to data container
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* @param size Container size in bytes
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*
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* @return the number of characters that have been read
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*/
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static int uart_cmsdk_apb_fifo_read(struct device *dev,
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uint8_t *rx_data, const int size)
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{
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volatile struct uart_cmsdk_apb *uart = UART_STRUCT(dev);
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/* No hardware FIFO present */
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if (size && uart->state & UART_RX_BF) {
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*rx_data = (unsigned char)uart->data;
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return 1;
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}
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return 0;
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}
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/**
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* @brief Enable TX interrupt
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*
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* @param dev UART device struct
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*
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* @return N/A
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*/
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static void uart_cmsdk_apb_irq_tx_enable(struct device *dev)
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{
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UART_STRUCT(dev)->ctrl |= UART_TX_IN_EN;
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}
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/**
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* @brief Disable TX interrupt
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*
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* @param dev UART device struct
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*
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* @return N/A
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*/
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static void uart_cmsdk_apb_irq_tx_disable(struct device *dev)
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{
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UART_STRUCT(dev)->ctrl &= ~UART_TX_IN_EN;
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}
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/**
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* @brief Verify if Tx interrupt has been raised
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*
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* @param dev UART device struct
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*
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* @return 1 if an interrupt is ready, 0 otherwise
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*/
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static int uart_cmsdk_apb_irq_tx_ready(struct device *dev)
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{
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return !(UART_STRUCT(dev)->state & UART_TX_BF);
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}
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/**
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* @brief Enable RX interrupt
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*
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* @param dev UART device struct
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*
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* @return N/A
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*/
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static void uart_cmsdk_apb_irq_rx_enable(struct device *dev)
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{
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UART_STRUCT(dev)->ctrl |= UART_RX_IN_EN;
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}
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/**
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* @brief Disable RX interrupt
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*
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* @param dev UART device struct
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*
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* @return N/A
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*/
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static void uart_cmsdk_apb_irq_rx_disable(struct device *dev)
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{
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UART_STRUCT(dev)->ctrl &= ~UART_RX_IN_EN;
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}
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/**
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* @brief Verify if Tx empty interrupt has been raised
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*
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* @param dev UART device struct
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*
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* @return 1 if an interrupt is ready, 0 otherwise
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*/
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static int uart_cmsdk_apb_irq_tx_empty(struct device *dev)
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{
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return uart_cmsdk_apb_irq_tx_ready(dev);
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}
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/**
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* @brief Verify if Rx interrupt has been raised
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*
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* @param dev UART device struct
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*
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* @return 1 if an interrupt is ready, 0 otherwise
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*/
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static int uart_cmsdk_apb_irq_rx_ready(struct device *dev)
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{
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return UART_STRUCT(dev)->state & UART_RX_BF;
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}
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/**
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* @brief Enable error interrupt
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*
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* @param dev UART device struct
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*
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* @return N/A
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*/
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static void uart_cmsdk_apb_irq_err_enable(struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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/**
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* @brief Disable error interrupt
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*
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* @param dev UART device struct
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*
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* @return N/A
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*/
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static void uart_cmsdk_apb_irq_err_disable(struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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/**
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* @brief Verify if Tx or Rx interrupt is pending
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*
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* @param dev UART device struct
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*
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* @return 1 if Tx or Rx interrupt is pending, 0 otherwise
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*/
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static int uart_cmsdk_apb_irq_is_pending(struct device *dev)
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{
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/* Return true if rx buffer full or tx buffer empty */
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return (UART_STRUCT(dev)->state & (UART_RX_BF | UART_TX_BF))
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!= UART_TX_BF;
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}
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/**
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* @brief Update the interrupt status
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*
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* @param dev UART device struct
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*
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* @return always 1
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*/
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static int uart_cmsdk_apb_irq_update(struct device *dev)
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{
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return 1;
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}
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/**
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* @brief Set the callback function pointer for an Interrupt.
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*
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* @param dev UART device structure
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* @param cb Callback function pointer.
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*
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* @return N/A
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*/
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static void uart_cmsdk_apb_irq_callback_set(struct device *dev,
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uart_irq_callback_t cb)
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{
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DEV_DATA(dev)->irq_cb = cb;
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}
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/**
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* @brief Interrupt service routine.
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*
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* Calls the callback function, if exists.
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*
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* @param arg argument to interrupt service routine.
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*
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* @return N/A
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*/
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void uart_cmsdk_apb_isr(void *arg)
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{
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struct device *dev = arg;
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volatile struct uart_cmsdk_apb *uart = UART_STRUCT(dev);
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struct uart_cmsdk_apb_dev_data *data = DEV_DATA(dev);
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/* Clear pending interrupts */
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uart->intclear = UART_RX_IN | UART_TX_IN;
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/* Verify if the callback has been registered */
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if (data->irq_cb) {
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data->irq_cb(dev);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static const struct uart_driver_api uart_cmsdk_apb_driver_api = {
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.poll_in = uart_cmsdk_apb_poll_in,
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.poll_out = uart_cmsdk_apb_poll_out,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_cmsdk_apb_fifo_fill,
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.fifo_read = uart_cmsdk_apb_fifo_read,
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.irq_tx_enable = uart_cmsdk_apb_irq_tx_enable,
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.irq_tx_disable = uart_cmsdk_apb_irq_tx_disable,
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.irq_tx_ready = uart_cmsdk_apb_irq_tx_ready,
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.irq_rx_enable = uart_cmsdk_apb_irq_rx_enable,
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.irq_rx_disable = uart_cmsdk_apb_irq_rx_disable,
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.irq_tx_empty = uart_cmsdk_apb_irq_tx_empty,
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.irq_rx_ready = uart_cmsdk_apb_irq_rx_ready,
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.irq_err_enable = uart_cmsdk_apb_irq_err_enable,
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.irq_err_disable = uart_cmsdk_apb_irq_err_disable,
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.irq_is_pending = uart_cmsdk_apb_irq_is_pending,
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.irq_update = uart_cmsdk_apb_irq_update,
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.irq_callback_set = uart_cmsdk_apb_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#ifdef CONFIG_UART_CMSDK_APB_PORT0
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void uart_cmsdk_apb_irq_config_func_0(struct device *dev);
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#endif
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static const struct uart_device_config uart_cmsdk_apb_dev_cfg_0 = {
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.base = (uint8_t *)CMSDK_APB_UART0,
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.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = uart_cmsdk_apb_irq_config_func_0,
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#endif
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};
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static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_0 = {
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.baud_rate = CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE,
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.uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
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.device = CMSDK_APB_UART0,},
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.uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
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.device = CMSDK_APB_UART0,},
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.uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
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.device = CMSDK_APB_UART0,},
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};
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DEVICE_AND_API_INIT(uart_cmsdk_apb_0,
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CONFIG_UART_CMSDK_APB_PORT0_NAME,
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&uart_cmsdk_apb_init,
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&uart_cmsdk_apb_dev_data_0,
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&uart_cmsdk_apb_dev_cfg_0, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&uart_cmsdk_apb_driver_api);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#ifdef CMSDK_APB_UART_0_IRQ
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static void uart_cmsdk_apb_irq_config_func_0(struct device *dev)
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{
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IRQ_CONNECT(CMSDK_APB_UART_0_IRQ,
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CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI,
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uart_cmsdk_apb_isr,
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DEVICE_GET(uart_cmsdk_apb_0),
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0);
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irq_enable(CMSDK_APB_UART_0_IRQ);
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}
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#else
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static void uart_cmsdk_apb_irq_config_func_0(struct device *dev)
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{
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IRQ_CONNECT(CMSDK_APB_UART_0_IRQ_TX,
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CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI,
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uart_cmsdk_apb_isr,
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DEVICE_GET(uart_cmsdk_apb_0),
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0);
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irq_enable(CMSDK_APB_UART_0_IRQ_TX);
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IRQ_CONNECT(CMSDK_APB_UART_0_IRQ_RX,
|
|
CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_0),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_0_IRQ_RX);
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* CONFIG_UART_CMSDK_APB_PORT0 */
|
|
|
|
#ifdef CONFIG_UART_CMSDK_APB_PORT1
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
static void uart_cmsdk_apb_irq_config_func_1(struct device *dev);
|
|
#endif
|
|
|
|
static const struct uart_device_config uart_cmsdk_apb_dev_cfg_1 = {
|
|
.base = (uint8_t *)CMSDK_APB_UART1,
|
|
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.irq_config_func = uart_cmsdk_apb_irq_config_func_1,
|
|
#endif
|
|
};
|
|
|
|
static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_1 = {
|
|
.baud_rate = CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE,
|
|
.uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
|
|
.device = CMSDK_APB_UART1,},
|
|
.uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
|
|
.device = CMSDK_APB_UART1,},
|
|
.uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
|
|
.device = CMSDK_APB_UART1,},
|
|
};
|
|
|
|
DEVICE_AND_API_INIT(uart_cmsdk_apb_1,
|
|
CONFIG_UART_CMSDK_APB_PORT1_NAME,
|
|
&uart_cmsdk_apb_init,
|
|
&uart_cmsdk_apb_dev_data_1,
|
|
&uart_cmsdk_apb_dev_cfg_1, PRE_KERNEL_1,
|
|
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
|
&uart_cmsdk_apb_driver_api);
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#ifdef CMSDK_APB_UART_1_IRQ
|
|
static void uart_cmsdk_apb_irq_config_func_1(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(CMSDK_APB_UART_1_IRQ,
|
|
CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_1),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_1_IRQ);
|
|
}
|
|
#else
|
|
static void uart_cmsdk_apb_irq_config_func_1(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(CMSDK_APB_UART_1_IRQ_TX,
|
|
CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_1),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_1_IRQ_TX);
|
|
|
|
IRQ_CONNECT(CMSDK_APB_UART_1_IRQ_RX,
|
|
CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_1),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_1_IRQ_RX);
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* CONFIG_UART_CMSDK_APB_PORT1 */
|
|
|
|
#ifdef CONFIG_UART_CMSDK_APB_PORT2
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
static void uart_cmsdk_apb_irq_config_func_2(struct device *dev);
|
|
#endif
|
|
|
|
static const struct uart_device_config uart_cmsdk_apb_dev_cfg_2 = {
|
|
.base = (uint8_t *)CMSDK_APB_UART2,
|
|
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.irq_config_func = uart_cmsdk_apb_irq_config_func_2,
|
|
#endif
|
|
};
|
|
|
|
static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_2 = {
|
|
.baud_rate = CONFIG_UART_CMSDK_APB_PORT2_BAUD_RATE,
|
|
.uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
|
|
.device = CMSDK_APB_UART2,},
|
|
.uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
|
|
.device = CMSDK_APB_UART2,},
|
|
.uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
|
|
.device = CMSDK_APB_UART2,},
|
|
};
|
|
|
|
DEVICE_AND_API_INIT(uart_cmsdk_apb_2,
|
|
CONFIG_UART_CMSDK_APB_PORT2_NAME,
|
|
&uart_cmsdk_apb_init,
|
|
&uart_cmsdk_apb_dev_data_2,
|
|
&uart_cmsdk_apb_dev_cfg_2, PRE_KERNEL_1,
|
|
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
|
&uart_cmsdk_apb_driver_api);
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#ifdef CMSDK_APB_UART_2_IRQ
|
|
static void uart_cmsdk_apb_irq_config_func_2(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(CMSDK_APB_UART_2_IRQ,
|
|
CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_2),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_2_IRQ);
|
|
}
|
|
#else
|
|
static void uart_cmsdk_apb_irq_config_func_2(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(CMSDK_APB_UART_2_IRQ_TX,
|
|
CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_2),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_2_IRQ_TX);
|
|
|
|
IRQ_CONNECT(CMSDK_APB_UART_2_IRQ_RX,
|
|
CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_2),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_2_IRQ_RX);
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* CONFIG_UART_CMSDK_APB_PORT2 */
|
|
|
|
#ifdef CONFIG_UART_CMSDK_APB_PORT3
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
static void uart_cmsdk_apb_irq_config_func_3(struct device *dev);
|
|
#endif
|
|
|
|
static const struct uart_device_config uart_cmsdk_apb_dev_cfg_3 = {
|
|
.base = (uint8_t *)CMSDK_APB_UART3,
|
|
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.irq_config_func = uart_cmsdk_apb_irq_config_func_3,
|
|
#endif
|
|
};
|
|
|
|
static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_3 = {
|
|
.baud_rate = CONFIG_UART_CMSDK_APB_PORT3_BAUD_RATE,
|
|
.uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
|
|
.device = CMSDK_APB_UART3,},
|
|
.uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
|
|
.device = CMSDK_APB_UART3,},
|
|
.uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
|
|
.device = CMSDK_APB_UART3,},
|
|
};
|
|
|
|
DEVICE_AND_API_INIT(uart_cmsdk_apb_3,
|
|
CONFIG_UART_CMSDK_APB_PORT3_NAME,
|
|
&uart_cmsdk_apb_init,
|
|
&uart_cmsdk_apb_dev_data_3,
|
|
&uart_cmsdk_apb_dev_cfg_3, PRE_KERNEL_1,
|
|
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
|
&uart_cmsdk_apb_driver_api);
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#ifdef CMSDK_APB_UART_3_IRQ
|
|
static void uart_cmsdk_apb_irq_config_func_3(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(CMSDK_APB_UART_3_IRQ,
|
|
CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_3),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_3_IRQ);
|
|
}
|
|
#else
|
|
static void uart_cmsdk_apb_irq_config_func_3(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(CMSDK_APB_UART_3_IRQ_TX,
|
|
CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_3),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_3_IRQ_TX);
|
|
|
|
IRQ_CONNECT(CMSDK_APB_UART_3_IRQ_RX,
|
|
CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_3),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_3_IRQ_RX);
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* CONFIG_UART_CMSDK_APB_PORT3 */
|
|
|
|
#ifdef CONFIG_UART_CMSDK_APB_PORT4
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
static void uart_cmsdk_apb_irq_config_func_4(struct device *dev);
|
|
#endif
|
|
|
|
static const struct uart_device_config uart_cmsdk_apb_dev_cfg_4 = {
|
|
.base = (uint8_t *)CMSDK_APB_UART4,
|
|
.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.irq_config_func = uart_cmsdk_apb_irq_config_func_4,
|
|
#endif
|
|
};
|
|
|
|
static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_4 = {
|
|
.baud_rate = CONFIG_UART_CMSDK_APB_PORT4_BAUD_RATE,
|
|
.uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
|
|
.device = CMSDK_APB_UART4,},
|
|
.uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
|
|
.device = CMSDK_APB_UART4,},
|
|
.uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
|
|
.device = CMSDK_APB_UART4,},
|
|
};
|
|
|
|
DEVICE_AND_API_INIT(uart_cmsdk_apb_4,
|
|
CONFIG_UART_CMSDK_APB_PORT4_NAME,
|
|
&uart_cmsdk_apb_init,
|
|
&uart_cmsdk_apb_dev_data_4,
|
|
&uart_cmsdk_apb_dev_cfg_4, PRE_KERNEL_1,
|
|
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
|
&uart_cmsdk_apb_driver_api);
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#ifdef CMSDK_APB_UART_4_IRQ
|
|
static void uart_cmsdk_apb_irq_config_func_4(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(CMSDK_APB_UART_4_IRQ,
|
|
CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_4),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_4_IRQ);
|
|
}
|
|
#else
|
|
static void uart_cmsdk_apb_irq_config_func_4(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(CMSDK_APB_UART_4_IRQ_TX,
|
|
CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_4),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_4_IRQ_TX);
|
|
|
|
IRQ_CONNECT(CMSDK_APB_UART_4_IRQ_RX,
|
|
CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI,
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_GET(uart_cmsdk_apb_4),
|
|
0);
|
|
irq_enable(CMSDK_APB_UART_4_IRQ_RX);
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* CONFIG_UART_CMSDK_APB_PORT4 */
|