76 lines
2.6 KiB
C
76 lines
2.6 KiB
C
/* cache.c - cache manipulation */
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This module contains functions for manipulation caches.
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <misc/util.h>
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#ifdef CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED
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#if (CONFIG_CACHE_LINE_SIZE == 0)
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#error Cannot use this implementation with a cache line size of 0
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#endif
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/*******************************************************************************
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*
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* _SysCacheFlush - flush a page to main memory
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*
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* No alignment is required for either <virt> or <size>, but since
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* _SysCacheFlush() iterates on the cache lines, a cache line alignment for both
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* is optimal.
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*
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* The cache line size is specified via the CONFIG_CACHE_LINE_SIZE kconfig
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* option.
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*
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* RETURNS: N/A
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*/
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void _SysCacheFlush(VIRT_ADDR virt, size_t size)
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{
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int end;
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size = ROUND_UP(size, CONFIG_CACHE_LINE_SIZE);
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end = virt + size;
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for (; virt < end; virt += CONFIG_CACHE_LINE_SIZE) {
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__asm__ volatile("clflush %0;\n\t" : : "m"(virt));
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}
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__asm__ volatile("mfence;\n\t");
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}
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#endif /* CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED */
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