54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <arch/arm/cortex_m/mpu/arm_mpu.h>
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#include "arm_mpu_mem_cfg.h"
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/* SoC Private Peripheral Bus */
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#define PPB_BASE 0xE0000000
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static struct arm_mpu_region mpu_regions[] = {
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/* Region 0 */
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MPU_REGION_ENTRY("FLASH_0",
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CONFIG_FLASH_BASE_ADDRESS,
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REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
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/* Region 1 */
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MPU_REGION_ENTRY("RAM_0",
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CONFIG_SRAM_BASE_ADDRESS,
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REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
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/* Region 2 */
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MPU_REGION_ENTRY("RAM_1",
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(CONFIG_SRAM_BASE_ADDRESS + REGION_SRAM_1_START),
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REGION_RAM_ATTR(REGION_SRAM_1_SIZE)),
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/* Region 3 */
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MPU_REGION_ENTRY("PERIPHERAL_0",
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APB1PERIPH_BASE,
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REGION_IO_ATTR(REGION_512M)),
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/* Region 4 */
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MPU_REGION_ENTRY("PPB_0",
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PPB_BASE,
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REGION_PPB_ATTR(REGION_256M)),
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#if defined(CONFIG_BL_APPLICATION)
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/* Region 5 */
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/*
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* The application booting from a bootloader has no access to the
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* bootloader region. This behavior can be changed at runtime by
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* the bootloader.
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*/
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MPU_REGION_ENTRY("BOOTLOADER_0",
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CONFIG_FLASH_BASE_ADDRESS,
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(NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE |
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REGION_32K | P_NA_U_NA)),
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#endif
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};
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struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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