133 lines
3.3 KiB
Plaintext
133 lines
3.3 KiB
Plaintext
# Kconfig - Atmel SAM E70 MCU series
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#
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# Copyright (c) 2016 Piotr Mienkowski
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "Atmel SAME70 MCU Selection"
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depends on SOC_SERIES_SAME70
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config SOC_PART_NUMBER_SAME70Q21
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bool "SAME70Q21"
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config SOC_PART_NUMBER_SAME70Q20
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bool "SAME70Q20"
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config SOC_PART_NUMBER_SAME70Q19
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bool "SAME70Q19"
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config SOC_PART_NUMBER_SAME70N21
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bool "SAME70N21"
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config SOC_PART_NUMBER_SAME70N20
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bool "SAME70N20"
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config SOC_PART_NUMBER_SAME70N19
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bool "SAME70N19"
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config SOC_PART_NUMBER_SAME70J21
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bool "SAME70J21"
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config SOC_PART_NUMBER_SAME70J20
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bool "SAME70J20"
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config SOC_PART_NUMBER_SAME70J19
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bool "SAME70J19"
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endchoice
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if SOC_SERIES_SAME70
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config SOC_ATMEL_SAME70_EXT_SLCK
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bool "Use external crystal oscillator for slow clock"
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default n
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help
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Say y if you want to use external 32 kHz crystal
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oscillator to drive the slow clock. Note that this
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adds a few seconds to boot time, as the crystal
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needs to stabilize after power-up.
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Says n if you do not need accurate and precise timers.
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The slow clock will be driven by the internal fast
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RC oscillator running at 32 kHz.
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config SOC_ATMEL_SAME70_EXT_MAINCK
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bool "Use external crystal oscillator for main clock"
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default n
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help
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The main clock is being used to drive the PLL, and
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thus driving the processor clock.
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Say y if you want to use external crystal oscillator
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to drive the main clock. Note that this adds about
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a second to boot time, as the crystal needs to
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stabilize after power-up.
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The crystal used here can be from 3 to 20 MHz.
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Says n here will use the internal fast RC oscillator
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running at 12 MHz.
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config SOC_ATMEL_SAME70_MDIV
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int "MDIV"
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default 2
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range 1 4
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help
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This divisor defines a ratio between processor clock (HCLK)
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and master clock (MCK):
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MCK = HCLK / MDIV
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config SOC_ATMEL_SAME70_PLLA_MULA
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int "PLL MULA"
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default 24
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range 1 62
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help
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This is the multiplier MULA used by the PLL.
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The processor clock is (MAINCK * (MULA + 1) / DIVA).
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Board config file can override this settings
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for a particular board.
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Setting MULA=0 would disable PLL at boot, this is currently
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not supported.
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With default of MULA == 24, and DIVA == 1,
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PLL is running at 25 times the main clock frequency.
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config SOC_ATMEL_SAME70_PLLA_DIVA
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int "PLL DIVA"
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default 1
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range 1 255
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help
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This is the divider DIVA used by the PLL.
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The processor clock is (MAINCK * (MULA + 1) / DIVA).
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Board config file can override this settings
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for a particular board.
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Setting DIVA=0 would disable PLL at boot, this is currently
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not supported.
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With default of MULA == 24, and DIVA == 1,
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PLL is running at 25 times the main clock frequency.
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config SOC_ATMEL_SAME70_WAIT_MODE
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bool "Go to Wait mode instead of Sleep mode"
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depends on SOC_ATMEL_SAME70_EXT_MAINCK
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default y if DEBUG
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help
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For JTAG debugging CPU clock (HCLK) should not stop. In order
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to achieve this, make CPU go to Wait mode instead of Sleep
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mode while using external crystal oscillator for main clock.
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config SOC_ATMEL_SAME70_DISABLE_ERASE_PIN
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bool "Disable ERASE pin"
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default 0
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help
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At reset ERASE pin is configured in System IO mode. Asserting the ERASE
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pin at '1' will completely erase Flash memory. Setting this option will
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switch the pin to general IO mode giving control of the pin to the GPIO
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module.
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endif # SOC_SERIES_SAME70
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