57 lines
1.4 KiB
C
57 lines
1.4 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_MCHP_PCR_H_
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#define _SOC_MCHP_PCR_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* slp_idx = [0, 4], bitpos = [0, 31] refer above */
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#define MCHP_XEC_PCR_SCR_ENCODE(slp_idx, bitpos, domain) \
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((((uint32_t)(domain) & 0xff) << 24) | (((bitpos) & 0x1f) << 3) \
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| ((uint32_t)(slp_idx) & 0x7))
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#define MCHP_XEC_PCR_SCR_GET_IDX(e) ((e) & 0x7u)
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#define MCHP_XEC_PCR_SCR_GET_BITPOS(e) (((e) & 0xf8u) >> 3)
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/* cpu clock divider */
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#define MCHP_XEC_CLK_CPU_MASK GENMASK(7, 0)
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#define MCHP_XEC_CLK_CPU_CLK_DIV_1 1u
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#define MCHP_XEC_CLK_CPU_CLK_DIV_2 2u
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#define MCHP_XEC_CLK_CPU_CLK_DIV_4 4u
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#define MCHP_XEC_CLK_CPU_CLK_DIV_8 8u
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#define MCHP_XEC_CLK_CPU_CLK_DIV_16 16u
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#define MCHP_XEC_CLK_CPU_CLK_DIV_48 48u
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/* slow clock divider */
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#define MCHP_XEC_CLK_SLOW_MASK GENMASK(8, 0)
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#define MCHP_XEC_CLK_SLOW_CLK_DIV_100K 480u
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#define MCHP_XEC_CLK_SRC_POS 24
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#define MCHP_XEC_CLK_SRC_MASK GENMASK(31, 24)
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#define MCHP_XEC_CLK_SRC_GET(n) \
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(((n) & MCHP_XEC_CLK_SRC_MASK) >> MCHP_XEC_CLK_SRC_POS)
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#define MCHP_XEC_CLK_SRC_SET(v, c) (((v) & ~MCHP_XEC_CLK_SRC_MASK) |\
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(((c) << MCHP_XEC_CLK_SRC_POS) & MCHP_XEC_CLK_SRC_MASK))
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/*
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* b[31:24] = clock source
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* b[23:0] = clock source specific format
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*/
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struct mchp_xec_pcr_clk_ctrl {
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uint32_t pcr_info;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_MCHP_PCR_H_ */
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