84 lines
3.1 KiB
C
84 lines
3.1 KiB
C
/*
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* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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/* SRAM0 (192kB) instruction cache+memory */
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#define SRAM0_IRAM_START 0x40070000
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#define SRAM0_CACHE_SIZE 0x10000
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#define SRAM0_SIZE 0x30000
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/* SRAM1 (128kB) instruction/data memory */
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#define SRAM1_IRAM_START 0x400a0000
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#define SRAM1_DRAM_START 0x3ffe0000
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#define SRAM1_SIZE 0x20000
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#define SRAM1_DRAM_END (SRAM1_DRAM_START + SRAM1_SIZE)
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#define SRAM1_DRAM_PROAPP_PRIV_SIZE 0x8000
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#define SRAM1_DRAM_USER_START 0x3ffe8000
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#define SRAM1_USER_SIZE (0x40000000 - SRAM1_DRAM_USER_START)
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/* SRAM2 (200kB) data memory */
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#define SRAM2_DRAM_START 0x3ffae000
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#define SRAM2_DRAM_SIZE 0x32000
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#define SRAM2_DRAM_SHM_SIZE 0x2000
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#define SRAM2_DRAM_END (SRAM2_DRAM_START + SRAM2_DRAM_SIZE)
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#define SRAM2_DRAM_USER_START (SRAM2_DRAM_START + SRAM2_DRAM_SHM_SIZE)
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#define SRAM2_DRAM_USER_SIZE (SRAM2_DRAM_END - SRAM2_DRAM_USER_START)
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/** Simplified memory map for the bootloader.
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* Make sure the bootloader can load into main memory without overwriting itself.
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*
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* ESP32 ROM static data usage is as follows:
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* - 0x3ffae000 - 0x3ffb0000 (Reserved: data memory for ROM functions)
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* - 0x3ffb0000 - 0x3ffe0000 (RAM bank 1 for application usage)
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* - 0x3ffe0000 - 0x3ffe0440 (Reserved: data memory for ROM PRO CPU)
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* - 0x3ffe3f20 - 0x3ffe4350 (Reserved: data memory for ROM APP CPU)
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* - 0x3ffe4350 - 0x3ffe5230 (BT shm buffers)
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* - 0x3ffe8000 - 0x3fffffff (RAM bank 2 for application usage)
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*/
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#define DRAM1_PROCPU_RESERVED_START 0x3ffe0000
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#define DRAM1_APPCPU_RESERVED_START 0x3ffe3f20
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#define DRAM1_BT_SHM_BUFFERS_START 0x3ffe4350
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#define DRAM1_BT_SHM_BUFFERS_END 0x3ffe5230
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/* Convert IRAM address to its DRAM counterpart in SRAM1 memory */
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#define SRAM1_IRAM_DRAM_CALC(addr_iram) ((addr_iram > SRAM1_IRAM_START) ? \
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(SRAM1_SIZE - (addr_iram - SRAM1_IRAM_START) + SRAM1_DRAM_START) : (SRAM1_DRAM_END))
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/* Convert DRAM address to its IRAM counterpart in SRAM1 memory */
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#define SRAM1_DRAM_IRAM_CALC(addr_dram) \
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(SRAM1_SIZE - (addr_dram - SRAM1_DRAM_START) + SRAM1_IRAM_START)
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/* Set bootloader segments size */
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#define BOOTLOADER_DRAM_SEG_LEN 0x7a00
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#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x4000
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#define BOOTLOADER_IRAM_SEG_LEN 0xa000
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/* Start of the lower region is determined by region size and the end of the higher region */
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#define BOOTLOADER_DRAM_SEG_START 0x3ffe8000
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#define BOOTLOADER_DRAM_SEG_END (BOOTLOADER_DRAM_SEG_START + BOOTLOADER_DRAM_SEG_LEN)
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#define BOOTLOADER_IRAM_LOADER_SEG_START 0x40078000
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#define BOOTLOADER_IRAM_SEG_START 0x400a0000
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/* Flash */
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#ifdef CONFIG_FLASH_SIZE
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#define FLASH_SIZE CONFIG_FLASH_SIZE
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#else
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#define FLASH_SIZE 0x400000
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#endif
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/* Cached memories */
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#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE
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#define IROM_SEG_ORG 0x400d0000
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#define IROM_SEG_LEN (FLASH_SIZE - 0x1000)
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#define DROM_SEG_ORG 0x3f400000
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#define DROM_SEG_LEN (FLASH_SIZE - 0x1000)
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/* AMP: TODO utilise memory for APPCPU */
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#ifndef CONFIG_SOC_ESP32_PROCPU
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#define APPCPU_IRAM_SIZE 0x20000
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#else
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#define APPCPU_IRAM_SIZE 0x8000
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#endif
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