8bdd45be47
What is changed? 1. Updated the data sync barrier to make sure the other parameters of `arm_cpu_boot_params` are updated before updating its member `mpidr` 2. Updated the MPIDR affinity level mask to account for affinity level 1 and 2 along with level 0. Why do we need this change? 1. As reported in issue #76182, on Cortex_A_R, the current code execution fails to consider the correct sequence of data sync barrier and cache maintenece for the code to work on non cache coherent cores in SMP enabled mode. The secondary cores are waiting in a loop for primary core to set `arm_cpu_boot_params.mpidr`. As soon as primary core set this, the secondary cores start reading other parameters from the `arm_cpu_boot_params` however, the existing position of DSB instruction doesn't guarantee that `arg`, `cpu_num` and other parameters of `arm_cpu_boot_params` would be updated before `mpidr` is udpated and this could lead to a unpredicatble behaviour so, we need to move the DSB instruction. 2. The affinity level mask is updated because it didn't account for level 1 to identify individual cores within a cluster and level 2 to identify different clusters within the system which can lead to an incorrect conversion between mpidr to core-id. Signed-off-by: Sudan Landge <sudan.landge@arm.com> |
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| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| common | ||
| mips | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.v1 | ||
| Kconfig.v2 | ||
| archs.yml | ||