395 lines
10 KiB
C
395 lines
10 KiB
C
/*
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* Copyright (c) 2017, Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* The logic here is adapted from SimpleLink SDK's I2CCC32XX.c module. */
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#include <kernel.h>
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#include <errno.h>
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#include <drivers/i2c.h>
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#include <soc.h>
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/* Driverlib includes */
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#include <inc/hw_memmap.h>
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#include <inc/hw_common_reg.h>
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#include <driverlib/rom.h>
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#include <driverlib/rom_map.h>
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#include <driverlib/i2c.h>
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#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(i2c_cc32xx);
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#include "i2c-priv.h"
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#define I2C_MASTER_CMD_BURST_RECEIVE_START_NACK I2C_MASTER_CMD_BURST_SEND_START
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#define I2C_MASTER_CMD_BURST_RECEIVE_STOP \
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I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
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#define I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK I2C_MASTER_CMD_BURST_SEND_CONT
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#define I2C_SEM_MASK \
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COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M
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#define I2C_SEM_TAKE \
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COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S
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#define IS_I2C_MSG_WRITE(flags) ((flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE)
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#define DEV_CFG(dev) \
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((const struct i2c_cc32xx_config *const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct i2c_cc32xx_data *const)(dev)->driver_data)
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#define DEV_BASE(dev) \
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((DEV_CFG(dev))->base)
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/* Since this driver does not explicitly enable the TX/RX FIFOs, there
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* are no interrupts received which can distinguish between read and write
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* completion.
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* So, we need the READ and WRITE state flags to determine whether the
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* completed transmission was started as a write or a read.
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* The ERROR flag is used to convey error status from the ISR back to the
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* I2C API without having to re-read I2C registers.
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*/
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enum i2c_cc32xx_state {
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/* I2C was primed for a write operation */
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I2C_CC32XX_WRITE_MODE,
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/* I2C was primed for a read operation */
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I2C_CC32XX_READ_MODE,
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/* I2C error occurred */
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I2C_CC32XX_ERROR = 0xFF
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};
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struct i2c_cc32xx_config {
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u32_t base;
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u32_t bitrate;
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unsigned int irq_no;
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};
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struct i2c_cc32xx_data {
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struct k_sem mutex;
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struct k_sem transfer_complete;
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volatile enum i2c_cc32xx_state state;
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struct i2c_msg msg; /* Cache msg for transfer state machine */
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u16_t slave_addr; /* Cache slave address for ISR use */
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};
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static void configure_i2c_irq(const struct i2c_cc32xx_config *config);
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static int i2c_cc32xx_configure(struct device *dev, u32_t dev_config_raw)
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{
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u32_t base = DEV_BASE(dev);
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u32_t bitrate_id;
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if (!(dev_config_raw & I2C_MODE_MASTER)) {
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return -EINVAL;
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}
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if (dev_config_raw & I2C_ADDR_10_BITS) {
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return -EINVAL;
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}
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switch (I2C_SPEED_GET(dev_config_raw)) {
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case I2C_SPEED_STANDARD:
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bitrate_id = 0U;
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break;
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case I2C_SPEED_FAST:
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bitrate_id = 1U;
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break;
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default:
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return -EINVAL;
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}
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MAP_I2CMasterInitExpClk(base, DT_I2C_0_CLOCK_FREQUENCY,
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bitrate_id);
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return 0;
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}
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static void i2c_cc32xx_prime_transfer(struct device *dev, struct i2c_msg *msg,
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u16_t addr)
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{
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struct i2c_cc32xx_data *data = DEV_DATA(dev);
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u32_t base = DEV_BASE(dev);
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/* Initialize internal counters and buf pointers: */
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data->msg = *msg;
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data->slave_addr = addr;
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/* Start transfer in Transmit mode */
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if (IS_I2C_MSG_WRITE(data->msg.flags)) {
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/* Specify the I2C slave address */
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MAP_I2CMasterSlaveAddrSet(base, addr, false);
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/* Update the I2C state */
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data->state = I2C_CC32XX_WRITE_MODE;
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/* Write data contents into data register */
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MAP_I2CMasterDataPut(base, *((data->msg.buf)++));
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/* Start the I2C transfer in master transmit mode */
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MAP_I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_START);
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} else {
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/* Start transfer in Receive mode */
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/* Specify the I2C slave address */
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MAP_I2CMasterSlaveAddrSet(base, addr, true);
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/* Update the I2C mode */
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data->state = I2C_CC32XX_READ_MODE;
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if (data->msg.len < 2) {
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/* Start the I2C transfer in master receive mode */
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MAP_I2CMasterControl(base,
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I2C_MASTER_CMD_BURST_RECEIVE_START_NACK);
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} else {
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/* Start the I2C transfer in burst receive mode */
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MAP_I2CMasterControl(base,
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I2C_MASTER_CMD_BURST_RECEIVE_START);
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}
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}
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}
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static int i2c_cc32xx_transfer(struct device *dev, struct i2c_msg *msgs,
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u8_t num_msgs, u16_t addr)
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{
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struct i2c_cc32xx_data *data = DEV_DATA(dev);
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int retval = 0;
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/* Acquire the driver mutex */
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k_sem_take(&data->mutex, K_FOREVER);
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/* Iterate over all the messages */
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for (int i = 0; i < num_msgs; i++) {
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/* Begin the transfer */
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i2c_cc32xx_prime_transfer(dev, msgs, addr);
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/* Wait for the transfer to complete */
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k_sem_take(&data->transfer_complete, K_FOREVER);
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/* Return an error if the transfer didn't complete */
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if (data->state == I2C_CC32XX_ERROR) {
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retval = -EIO;
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break;
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}
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/* Move to the next message */
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msgs++;
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}
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/* Release the mutex */
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k_sem_give(&data->mutex);
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return retval;
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}
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static void i2c_cc32xx_isr_handle_write(u32_t base,
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struct i2c_cc32xx_data *data)
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{
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/* Decrement write Counter */
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data->msg.len--;
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/* Check if more data needs to be sent */
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if (data->msg.len) {
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/* Write data contents into data register */
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MAP_I2CMasterDataPut(base, *(data->msg.buf));
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data->msg.buf++;
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if (data->msg.len < 2) {
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/* Everything has been sent, nothing to receive */
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/* Send last byte with STOP bit */
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MAP_I2CMasterControl(base,
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I2C_MASTER_CMD_BURST_SEND_FINISH);
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} else {
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/*
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* Either there is more data to be transmitted or some
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* data needs to be received next
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*/
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MAP_I2CMasterControl(base,
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I2C_MASTER_CMD_BURST_SEND_CONT);
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}
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} else {
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/*
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* No more data needs to be sent, so follow up with
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* a STOP bit.
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*/
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MAP_I2CMasterControl(base,
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I2C_MASTER_CMD_BURST_RECEIVE_STOP);
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}
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}
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static void i2c_cc32xx_isr_handle_read(u32_t base,
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struct i2c_cc32xx_data *data)
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{
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/* Save the received data */
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*(data->msg.buf) = MAP_I2CMasterDataGet(base);
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data->msg.buf++;
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/* Check if any data needs to be received */
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data->msg.len--;
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if (data->msg.len) {
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if (data->msg.len > 1) {
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/* More data to be received */
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MAP_I2CMasterControl(base,
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I2C_MASTER_CMD_BURST_RECEIVE_CONT);
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} else {
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/*
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* Send NACK because it's the last byte to be received
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*/
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MAP_I2CMasterControl(base,
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I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK);
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}
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} else {
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/*
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* No more data needs to be received, so follow up with a
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* STOP bit
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*/
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MAP_I2CMasterControl(base,
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I2C_MASTER_CMD_BURST_RECEIVE_STOP);
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}
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}
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static void i2c_cc32xx_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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u32_t base = DEV_BASE(dev);
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struct i2c_cc32xx_data *data = DEV_DATA(dev);
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u32_t err_status;
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u32_t int_status;
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/* Get the error status of the I2C controller */
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err_status = MAP_I2CMasterErr(base);
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/* Get interrupt cause (from I2CMRIS (raw interrupt) reg): */
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int_status = MAP_I2CMasterIntStatusEx(base, 0);
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/* Clear interrupt source to avoid additional interrupts */
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MAP_I2CMasterIntClearEx(base, int_status);
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LOG_DBG("primed state: %d; err_status: 0x%x; int_status: 0x%x",
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data->state, err_status, int_status);
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/* Handle errors: */
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if ((err_status != I2C_MASTER_ERR_NONE) ||
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(int_status &
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(I2C_MASTER_INT_ARB_LOST | I2C_MASTER_INT_TIMEOUT))) {
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/* Set so API can report I/O error: */
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data->state = I2C_CC32XX_ERROR;
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if (!(err_status & (I2C_MASTER_ERR_ARB_LOST |
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I2C_MASTER_ERR_ADDR_ACK))) {
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/* Send a STOP bit to end I2C communications */
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/*
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* I2C_MASTER_CMD_BURST_SEND_ERROR_STOP -and-
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* I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
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* have the same values
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*/
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MAP_I2CMasterControl(base,
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I2C_MASTER_CMD_BURST_SEND_ERROR_STOP);
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}
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/* Indicate transfer complete */
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k_sem_give(&data->transfer_complete);
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/* Handle Stop: */
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} else if (int_status & I2C_MASTER_INT_STOP) {
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/* Indicate transfer complete */
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k_sem_give(&data->transfer_complete);
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/* Handle (read or write) transmit complete: */
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} else if (int_status & (I2C_MASTER_INT_DATA | I2C_MASTER_INT_START)) {
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if (data->state == I2C_CC32XX_WRITE_MODE) {
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i2c_cc32xx_isr_handle_write(base, data);
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}
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if (data->state == I2C_CC32XX_READ_MODE) {
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i2c_cc32xx_isr_handle_read(base, data);
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}
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/* Some unanticipated H/W state: */
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} else {
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__ASSERT(1, "Unanticipated I2C Interrupt!");
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data->state = I2C_CC32XX_ERROR;
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k_sem_give(&data->transfer_complete);
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}
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}
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static int i2c_cc32xx_init(struct device *dev)
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{
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u32_t base = DEV_BASE(dev);
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const struct i2c_cc32xx_config *config = DEV_CFG(dev);
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struct i2c_cc32xx_data *data = DEV_DATA(dev);
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u32_t bitrate_cfg;
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int error;
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u32_t regval;
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k_sem_init(&data->mutex, 1, UINT_MAX);
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k_sem_init(&data->transfer_complete, 0, UINT_MAX);
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/* In case of app restart: disable I2C module, clear NVIC interrupt */
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/* Note: this was done *during* pinmux setup in SimpleLink SDK. */
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MAP_I2CMasterDisable(base);
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/* Clear exception INT_I2CA0 */
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MAP_IntPendClear((unsigned long)(config->irq_no + 16));
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configure_i2c_irq(config);
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/* Take I2C hardware semaphore. */
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regval = HWREG(COMMON_REG_BASE);
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regval = (regval & ~I2C_SEM_MASK) | (0x01 << I2C_SEM_TAKE);
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HWREG(COMMON_REG_BASE) = regval;
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/* Set to default configuration: */
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bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
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error = i2c_cc32xx_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
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if (error) {
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return error;
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}
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/* Clear any pending interrupts */
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MAP_I2CMasterIntClear(base);
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/* Enable the I2C Master for operation */
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MAP_I2CMasterEnable(base);
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/* Unmask I2C interrupts */
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MAP_I2CMasterIntEnable(base);
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return 0;
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}
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static const struct i2c_driver_api i2c_cc32xx_driver_api = {
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.configure = i2c_cc32xx_configure,
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.transfer = i2c_cc32xx_transfer,
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};
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static const struct i2c_cc32xx_config i2c_cc32xx_config = {
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.base = DT_I2C_0_BASE_ADDRESS,
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.bitrate = DT_I2C_0_BITRATE,
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.irq_no = DT_I2C_0_IRQ,
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};
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static struct i2c_cc32xx_data i2c_cc32xx_data;
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DEVICE_AND_API_INIT(i2c_cc32xx, DT_I2C_0_LABEL, &i2c_cc32xx_init,
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&i2c_cc32xx_data, &i2c_cc32xx_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&i2c_cc32xx_driver_api);
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static void configure_i2c_irq(const struct i2c_cc32xx_config *config)
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{
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IRQ_CONNECT(DT_I2C_0_IRQ,
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DT_I2C_0_IRQ_PRIORITY,
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i2c_cc32xx_isr, DEVICE_GET(i2c_cc32xx), 0);
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irq_enable(config->irq_no);
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}
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