71 lines
1.7 KiB
C
71 lines
1.7 KiB
C
/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC__H_
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#define _SOC__H_
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/* Do not let CMSIS to handle GIC and Timer */
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#include <stdint.h>
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#define __GIC_PRESENT 0
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#define __TIM_PRESENT 0
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/* Global system counter */
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#define CNTCR_EN BIT(0)
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#define CNTCR_HDBG BIT(1)
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/* Safety area protect register */
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#define PRCRS_CLK BIT(0)
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#define PRCRS_LPC_RESET BIT(1)
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#define PRCRS_GPIO BIT(2)
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#define PRCRS_SYS_CTRL BIT(3)
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/* Non-safety area protect register */
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#define PRCRN_PRC0 BIT(0)
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#define PRCRN_PRC1 BIT(1)
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#define PRCRN_PRC2 BIT(2)
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#define SCI4ASYNCSEL BIT(31)
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#define SCI3ASYNCSEL BIT(30)
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#define SCI2ASYNCSEL BIT(29)
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#define SCI1ASYNCSEL BIT(28)
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#define SCI0ASYNCSEL BIT(27)
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#define SPI2ASYNCSEL BIT(26)
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#define SPI1ASYNCSEL BIT(25)
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#define SPI0ASYNCSEL BIT(24)
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#define CLMASEL BIT(22)
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#define PHYSEL BIT(21)
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#define FSELCANFD BIT(20)
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#define DIVSELXSPI1 BIT(14)
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#define DIVSELXSPI0 BIT(6)
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#define CKIO_DEFAULT BIT(17)
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#define FSELXSPI1_DEFAULT GENMASK(10, 9)
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#define FSELXSPI0_DEFAULT GENMASK(2, 1)
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#define SCI5ASYNCSEL BIT(25)
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#define SPI3ASYNCSEL BIT(24)
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#define DIVSELSUB BIT(5)
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#define FSELCPU1_DEFAULT 0b10 << 2
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#define FSELCPU0_DEFAULT 0b10 << 0
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/* PRC Key Code - this value is required to allow any write operation
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* to the PRCRS / PRCRN registers.
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* See section 10.2 of the RZ/T2M User's Manual: Hardware.
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*/
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#define PRC_KEY_CODE 0xa500
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void rzt2m_unlock_prcrn(uint32_t mask);
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void rzt2m_lock_prcrn(uint32_t mask);
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void rzt2m_unlock_prcrs(uint32_t mask);
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void rzt2m_lock_prcrs(uint32_t mask);
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void rzt2m_set_sckcr2(uint32_t mask);
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uint32_t rzt2m_get_sckcr2(void);
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void rzt2m_set_sckcr(uint32_t mask);
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uint32_t rzt2m_get_sckcr(void);
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#endif /* _SOC__H_ */
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