119 lines
2.4 KiB
C
119 lines
2.4 KiB
C
/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <stdint.h>
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#include <zephyr/drivers/syscon.h>
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#include "soc.h"
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#include <zephyr/sys/util_macro.h>
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static const struct device *const prcrn_dev = DEVICE_DT_GET(DT_NODELABEL(prcrn));
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static const struct device *const prcrs_dev = DEVICE_DT_GET(DT_NODELABEL(prcrs));
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static const struct device *const sckcr_dev = DEVICE_DT_GET(DT_NODELABEL(sckcr));
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static const struct device *const sckcr2_dev = DEVICE_DT_GET(DT_NODELABEL(sckcr2));
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void rzt2m_unlock_prcrn(uint32_t mask)
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{
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uint32_t prcrn;
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syscon_read_reg(prcrn_dev, 0, &prcrn);
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prcrn |= PRC_KEY_CODE | mask;
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syscon_write_reg(prcrn_dev, 0, prcrn);
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}
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void rzt2m_lock_prcrn(uint32_t mask)
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{
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uint32_t prcrn;
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syscon_read_reg(prcrn_dev, 0, &prcrn);
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prcrn &= ~mask;
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prcrn |= PRC_KEY_CODE;
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syscon_write_reg(prcrn_dev, 0, prcrn);
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}
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void rzt2m_unlock_prcrs(uint32_t mask)
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{
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uint32_t prcrs;
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syscon_read_reg(prcrs_dev, 0, &prcrs);
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prcrs |= PRC_KEY_CODE | mask;
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syscon_write_reg(prcrs_dev, 0, prcrs);
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}
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void rzt2m_lock_prcrs(uint32_t mask)
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{
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uint32_t prcrs;
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syscon_read_reg(prcrs_dev, 0, &prcrs);
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prcrs &= ~mask;
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prcrs |= PRC_KEY_CODE;
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syscon_write_reg(prcrs_dev, 0, prcrs);
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}
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void rzt2m_set_sckcr2(uint32_t mask)
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{
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syscon_write_reg(sckcr2_dev, 0, mask);
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}
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uint32_t rzt2m_get_sckcr2(void)
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{
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uint32_t reg;
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syscon_read_reg(sckcr2_dev, 0, ®);
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return reg;
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}
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void rzt2m_set_sckcr(uint32_t mask)
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{
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syscon_write_reg(sckcr_dev, 0, mask);
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}
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uint32_t rzt2m_get_sckcr(void)
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{
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uint32_t reg;
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syscon_read_reg(sckcr_dev, 0, ®);
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return reg;
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}
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void rzt2m_enable_counters(void)
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{
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(gsc));
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syscon_write_reg(dev, 0, CNTCR_EN);
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}
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void soc_early_init_hook(void)
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{
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/* Unlock the Protect Registers
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* so that device drivers can access configuration registers of peripherals.
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*/
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/* After the device drivers are done, lock the Protect Registers. */
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rzt2m_unlock_prcrs(PRCRS_GPIO | PRCRS_CLK);
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rzt2m_unlock_prcrn(PRCRN_PRC1 | PRCRN_PRC2 | PRCRN_PRC0);
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/* Reset the System Clock Control Registers to default values */
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rzt2m_set_sckcr(
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CLMASEL |
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PHYSEL |
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FSELCANFD |
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FSELXSPI0_DEFAULT |
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FSELXSPI1_DEFAULT |
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CKIO_DEFAULT
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);
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rzt2m_set_sckcr2(FSELCPU0_DEFAULT | FSELCPU1_DEFAULT);
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rzt2m_lock_prcrs(PRCRS_GPIO | PRCRS_CLK);
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rzt2m_lock_prcrn(PRCRN_PRC1 | PRCRN_PRC2 | PRCRN_PRC0);
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rzt2m_enable_counters();
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}
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