36 lines
969 B
C
36 lines
969 B
C
/*
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* Copyright (c) 2023 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <xtensa/config/core-isa.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/arch/xtensa/xtensa_mmu.h>
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#include <zephyr/sys/util.h>
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const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = {
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{
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.start = (uint32_t)XCHAL_VECBASE_RESET_VADDR,
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.end = (uint32_t)CONFIG_SRAM_OFFSET,
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.attrs = XTENSA_MMU_PERM_X | XTENSA_MMU_CACHED_WB | XTENSA_MMU_MAP_SHARED,
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.name = "vecbase",
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},
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{
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/* The ROM is 32MB but the address wraps around back to 0x00000000.
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* So just skip the last page so we don't have to deal with integer
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* overflow.
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*/
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.start = (uint32_t)DT_REG_ADDR(DT_NODELABEL(rom0)),
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.end = (uint32_t)DT_REG_ADDR(DT_NODELABEL(rom0)) +
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(uint32_t)DT_REG_SIZE(DT_NODELABEL(rom0)),
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.attrs = XTENSA_MMU_PERM_X | XTENSA_MMU_CACHED_WB,
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.name = "rom",
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},
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};
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int xtensa_soc_mmu_ranges_num = ARRAY_SIZE(xtensa_soc_mmu_ranges);
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