264 lines
6.7 KiB
C
264 lines
6.7 KiB
C
/*
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* Copyright (c) 2018-2023 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <limits.h>
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#include <zephyr/init.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/sys_clock.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/irq.h>
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/* andestech,machine-timer */
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#if DT_HAS_COMPAT_STATUS_OKAY(andestech_machine_timer)
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#define DT_DRV_COMPAT andestech_machine_timer
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#define MTIME_REG DT_INST_REG_ADDR(0)
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#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8)
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#define TIMER_IRQN DT_INST_IRQN(0)
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/* neorv32-machine-timer */
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#elif DT_HAS_COMPAT_STATUS_OKAY(neorv32_machine_timer)
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#define DT_DRV_COMPAT neorv32_machine_timer
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#define MTIME_REG DT_INST_REG_ADDR(0)
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#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8)
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#define TIMER_IRQN DT_INST_IRQN(0)
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/* nuclei,systimer */
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#elif DT_HAS_COMPAT_STATUS_OKAY(nuclei_systimer)
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#define DT_DRV_COMPAT nuclei_systimer
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#define MTIME_REG DT_INST_REG_ADDR(0)
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#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8)
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#define TIMER_IRQN DT_INST_IRQ_BY_IDX(0, 1, irq)
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/* sifive,clint0 */
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#elif DT_HAS_COMPAT_STATUS_OKAY(sifive_clint0)
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#define DT_DRV_COMPAT sifive_clint0
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#define MTIME_REG (DT_INST_REG_ADDR(0) + 0xbff8U)
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#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 0x4000U)
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#define TIMER_IRQN DT_INST_IRQ_BY_IDX(0, 1, irq)
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/* telink,machine-timer */
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#elif DT_HAS_COMPAT_STATUS_OKAY(telink_machine_timer)
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#define DT_DRV_COMPAT telink_machine_timer
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#define MTIME_REG DT_INST_REG_ADDR(0)
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#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8)
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#define TIMER_IRQN DT_INST_IRQN(0)
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/* lowrisc,machine-timer */
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#elif DT_HAS_COMPAT_STATUS_OKAY(lowrisc_machine_timer)
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#define DT_DRV_COMPAT lowrisc_machine_timer
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#define MTIME_REG (DT_INST_REG_ADDR(0) + 0x110)
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#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 0x118)
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#define TIMER_IRQN DT_INST_IRQN(0)
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/* niosv-machine-timer */
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#elif DT_HAS_COMPAT_STATUS_OKAY(niosv_machine_timer)
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#define DT_DRV_COMPAT niosv_machine_timer
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#define MTIMECMP_REG DT_INST_REG_ADDR(0)
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#define MTIME_REG (DT_INST_REG_ADDR(0) + 8)
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#define TIMER_IRQN DT_INST_IRQN(0)
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/* scr,machine-timer*/
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#elif DT_HAS_COMPAT_STATUS_OKAY(scr_machine_timer)
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#define DT_DRV_COMPAT scr_machine_timer
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#define MTIMER_HAS_DIVIDER
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#define MTIMEDIV_REG (DT_INST_REG_ADDR_U64(0) + 4)
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#define MTIME_REG (DT_INST_REG_ADDR_U64(0) + 8)
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#define MTIMECMP_REG (DT_INST_REG_ADDR_U64(0) + 16)
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#define TIMER_IRQN DT_INST_IRQN(0)
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#endif
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#define CYC_PER_TICK (uint32_t)(sys_clock_hw_cycles_per_sec() \
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/* the unsigned long cast limits divisions to native CPU register width */
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#define cycle_diff_t unsigned long
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#define CYCLE_DIFF_MAX (~(cycle_diff_t)0)
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/*
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* We have two constraints on the maximum number of cycles we can wait for.
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*
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* 1) sys_clock_announce() accepts at most INT32_MAX ticks.
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*
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* 2) The number of cycles between two reports must fit in a cycle_diff_t
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* variable before converting it to ticks.
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*
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* Then:
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*
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* 3) Pick the smallest between (1) and (2).
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*
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* 4) Take into account some room for the unavoidable IRQ servicing latency.
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* Let's use 3/4 of the max range.
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*
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* Finally let's add the LSB value to the result so to clear out a bunch of
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* consecutive set bits coming from the original max values to produce a
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* nicer literal for assembly generation.
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*/
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#define CYCLES_MAX_1 ((uint64_t)INT32_MAX * (uint64_t)CYC_PER_TICK)
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#define CYCLES_MAX_2 ((uint64_t)CYCLE_DIFF_MAX)
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#define CYCLES_MAX_3 MIN(CYCLES_MAX_1, CYCLES_MAX_2)
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#define CYCLES_MAX_4 (CYCLES_MAX_3 / 2 + CYCLES_MAX_3 / 4)
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#define CYCLES_MAX (CYCLES_MAX_4 + LSB_GET(CYCLES_MAX_4))
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static struct k_spinlock lock;
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static uint64_t last_count;
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static uint64_t last_ticks;
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static uint32_t last_elapsed;
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#if defined(CONFIG_TEST)
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const int32_t z_sys_timer_irq_for_test = TIMER_IRQN;
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#endif
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static uintptr_t get_hart_mtimecmp(void)
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{
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return MTIMECMP_REG + (arch_proc_id() * 8);
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}
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static void set_mtimecmp(uint64_t time)
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{
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#ifdef CONFIG_64BIT
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*(volatile uint64_t *)get_hart_mtimecmp() = time;
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#else
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volatile uint32_t *r = (uint32_t *)get_hart_mtimecmp();
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/* Per spec, the RISC-V MTIME/MTIMECMP registers are 64 bit,
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* but are NOT internally latched for multiword transfers. So
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* we have to be careful about sequencing to avoid triggering
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* spurious interrupts: always set the high word to a max
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* value first.
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*/
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r[1] = 0xffffffff;
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r[0] = (uint32_t)time;
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r[1] = (uint32_t)(time >> 32);
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#endif
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}
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static void set_divider(void)
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{
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#ifdef MTIMER_HAS_DIVIDER
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*(volatile uint32_t *)MTIMEDIV_REG =
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CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER;
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#endif
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}
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static uint64_t mtime(void)
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{
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#ifdef CONFIG_64BIT
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return *(volatile uint64_t *)MTIME_REG;
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#else
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volatile uint32_t *r = (uint32_t *)MTIME_REG;
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uint32_t lo, hi;
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/* Likewise, must guard against rollover when reading */
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do {
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hi = r[1];
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lo = r[0];
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} while (r[1] != hi);
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return (((uint64_t)hi) << 32) | lo;
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#endif
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}
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static void timer_isr(const void *arg)
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{
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ARG_UNUSED(arg);
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint64_t now = mtime();
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uint64_t dcycles = now - last_count;
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uint32_t dticks = (cycle_diff_t)dcycles / CYC_PER_TICK;
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last_count += (cycle_diff_t)dticks * CYC_PER_TICK;
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last_ticks += dticks;
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last_elapsed = 0;
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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uint64_t next = last_count + CYC_PER_TICK;
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set_mtimecmp(next);
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}
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k_spin_unlock(&lock, key);
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sys_clock_announce(dticks);
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}
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint64_t cyc;
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if (ticks == K_TICKS_FOREVER) {
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cyc = last_count + CYCLES_MAX;
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} else {
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cyc = (last_ticks + last_elapsed + ticks) * CYC_PER_TICK;
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if ((cyc - last_count) > CYCLES_MAX) {
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cyc = last_count + CYCLES_MAX;
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}
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}
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set_mtimecmp(cyc);
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k_spin_unlock(&lock, key);
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}
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uint32_t sys_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint64_t now = mtime();
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uint64_t dcycles = now - last_count;
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uint32_t dticks = (cycle_diff_t)dcycles / CYC_PER_TICK;
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last_elapsed = dticks;
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k_spin_unlock(&lock, key);
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return dticks;
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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return ((uint32_t)mtime()) << CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER;
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}
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uint64_t sys_clock_cycle_get_64(void)
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{
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return mtime() << CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER;
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}
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static int sys_clock_driver_init(void)
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{
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set_divider();
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IRQ_CONNECT(TIMER_IRQN, 0, timer_isr, NULL, 0);
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last_ticks = mtime() / CYC_PER_TICK;
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last_count = last_ticks * CYC_PER_TICK;
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set_mtimecmp(last_count + CYC_PER_TICK);
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irq_enable(TIMER_IRQN);
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return 0;
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}
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#ifdef CONFIG_SMP
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void smp_timer_init(void)
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{
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set_mtimecmp(last_count + CYC_PER_TICK);
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irq_enable(TIMER_IRQN);
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}
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#endif
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
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CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
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