141 lines
3.9 KiB
C
141 lines
3.9 KiB
C
/*
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* Copyright (c) 2021 Telink Semiconductor
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT telink_b91_pwm
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#include <pwm.h>
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#include <clock.h>
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/drivers/pinctrl.h>
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struct pwm_b91_config {
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const struct pinctrl_dev_config *pcfg;
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uint32_t clock_frequency;
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uint8_t channels;
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uint8_t clk32k_ch_enable;
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};
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/* API implementation: init */
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static int pwm_b91_init(const struct device *dev)
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{
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const struct pwm_b91_config *config = dev->config;
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uint32_t status = 0;
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uint8_t clk_32k_en = 0;
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uint32_t pwm_clk_div = 0;
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/* Calculate and check PWM clock divider */
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pwm_clk_div = sys_clk.pclk * 1000 * 1000 / config->clock_frequency - 1;
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if (pwm_clk_div > 255) {
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return -EINVAL;
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}
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/* Set PWM Peripheral clock */
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pwm_set_clk((unsigned char) (pwm_clk_div & 0xFF));
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/* Set PWM 32k Channel clock if enabled */
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clk_32k_en |= (config->clk32k_ch_enable & BIT(0)) ? PWM_CLOCK_32K_CHN_PWM0 : 0;
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clk_32k_en |= (config->clk32k_ch_enable & BIT(1)) ? PWM_CLOCK_32K_CHN_PWM1 : 0;
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clk_32k_en |= (config->clk32k_ch_enable & BIT(2)) ? PWM_CLOCK_32K_CHN_PWM2 : 0;
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clk_32k_en |= (config->clk32k_ch_enable & BIT(3)) ? PWM_CLOCK_32K_CHN_PWM3 : 0;
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clk_32k_en |= (config->clk32k_ch_enable & BIT(4)) ? PWM_CLOCK_32K_CHN_PWM4 : 0;
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clk_32k_en |= (config->clk32k_ch_enable & BIT(5)) ? PWM_CLOCK_32K_CHN_PWM5 : 0;
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pwm_32k_chn_en(clk_32k_en);
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/* Config PWM pins */
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status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (status < 0) {
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return status;
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}
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return 0;
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}
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/* API implementation: set_cycles */
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static int pwm_b91_set_cycles(const struct device *dev, uint32_t channel,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct pwm_b91_config *config = dev->config;
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/* check pwm channel */
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if (channel >= config->channels) {
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return -EINVAL;
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}
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/* check size of pulse and period (2 bytes) */
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if ((period_cycles > 0xFFFFu) ||
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(pulse_cycles > 0xFFFFu)) {
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return -EINVAL;
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}
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/* set polarity */
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if (flags & PWM_POLARITY_INVERTED) {
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pwm_invert_en(channel);
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} else {
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pwm_invert_dis(channel);
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}
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/* set pulse and period */
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pwm_set_tcmp(channel, pulse_cycles);
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pwm_set_tmax(channel, period_cycles);
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/* start pwm */
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pwm_start(channel);
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return 0;
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}
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/* API implementation: get_cycles_per_sec */
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static int pwm_b91_get_cycles_per_sec(const struct device *dev,
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uint32_t channel, uint64_t *cycles)
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{
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const struct pwm_b91_config *config = dev->config;
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/* check pwm channel */
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if (channel >= config->channels) {
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return -EINVAL;
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}
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if ((config->clk32k_ch_enable & BIT(channel)) != 0U) {
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*cycles = 32000u;
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} else {
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*cycles = sys_clk.pclk * 1000 * 1000 / (reg_pwm_clkdiv + 1);
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}
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return 0;
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}
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/* PWM driver APIs structure */
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static const struct pwm_driver_api pwm_b91_driver_api = {
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.set_cycles = pwm_b91_set_cycles,
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.get_cycles_per_sec = pwm_b91_get_cycles_per_sec,
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};
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/* PWM driver registration */
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#define PWM_B91_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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\
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static const struct pwm_b91_config config##n = { \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.clock_frequency = DT_INST_PROP(n, clock_frequency), \
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.channels = DT_INST_PROP(n, channels), \
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.clk32k_ch_enable = \
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((DT_INST_PROP(n, clk32k_ch0_enable) << 0U) | \
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(DT_INST_PROP(n, clk32k_ch1_enable) << 1U) | \
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(DT_INST_PROP(n, clk32k_ch2_enable) << 2U) | \
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(DT_INST_PROP(n, clk32k_ch3_enable) << 3U) | \
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(DT_INST_PROP(n, clk32k_ch4_enable) << 4U) | \
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(DT_INST_PROP(n, clk32k_ch5_enable) << 5U)), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, pwm_b91_init, \
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NULL, NULL, &config##n, \
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POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
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&pwm_b91_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_B91_INIT)
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