415 lines
8.7 KiB
C
415 lines
8.7 KiB
C
/*
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* Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam0_eic
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#include <zephyr/device.h>
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#include <zephyr/irq.h>
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#include <soc.h>
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#include <zephyr/drivers/interrupt_controller/sam0_eic.h>
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#include "intc_sam0_eic_priv.h"
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struct sam0_eic_line_assignment {
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uint8_t pin : 5;
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uint8_t port : 2;
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uint8_t enabled : 1;
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};
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struct sam0_eic_port_data {
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sam0_eic_callback_t cb;
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void *data;
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};
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struct sam0_eic_data {
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struct sam0_eic_port_data ports[PORT_GROUPS];
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struct sam0_eic_line_assignment lines[EIC_EXTINT_NUM];
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};
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static void wait_synchronization(void)
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{
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#ifdef REG_EIC_SYNCBUSY
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while (EIC->SYNCBUSY.reg) {
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}
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#else
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while (EIC->STATUS.bit.SYNCBUSY) {
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}
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#endif
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}
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static inline void set_eic_enable(bool on)
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{
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#ifdef REG_EIC_CTRLA
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EIC->CTRLA.bit.ENABLE = on;
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#else
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EIC->CTRL.bit.ENABLE = on;
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#endif
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}
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static void sam0_eic_isr(const struct device *dev)
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{
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struct sam0_eic_data *const dev_data = dev->data;
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uint16_t bits = EIC->INTFLAG.reg;
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uint32_t line_index;
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/* Acknowledge all interrupts */
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EIC->INTFLAG.reg = bits;
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/* No clz on M0, so just do a quick test */
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#if __CORTEX_M >= 3
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line_index = __CLZ(__RBIT(bits));
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bits >>= line_index;
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#else
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if (bits & 0xFF) {
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line_index = 0;
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} else {
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line_index = 8;
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bits >>= 8;
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}
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#endif
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/*
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* Map the EIC lines to the port pin masks based on which port is
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* selected in the line data.
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*/
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for (; bits; bits >>= 1, line_index++) {
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if (!(bits & 1)) {
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continue;
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}
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/*
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* These could be aggregated together into one call, but
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* usually on a single one will be set, so just call them
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* one by one.
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*/
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struct sam0_eic_line_assignment *line_assignment =
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&dev_data->lines[line_index];
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struct sam0_eic_port_data *port_data =
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&dev_data->ports[line_assignment->port];
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port_data->cb(BIT(line_assignment->pin), port_data->data);
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}
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}
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int sam0_eic_acquire(int port, int pin, enum sam0_eic_trigger trigger,
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bool filter, sam0_eic_callback_t cb, void *data)
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{
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const struct device *const dev = DEVICE_DT_INST_GET(0);
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struct sam0_eic_data *dev_data = dev->data;
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struct sam0_eic_port_data *port_data;
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struct sam0_eic_line_assignment *line_assignment;
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uint32_t mask;
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int line_index;
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int config_index;
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int config_shift;
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unsigned int key;
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uint32_t config;
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line_index = sam0_eic_map_to_line(port, pin);
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if (line_index < 0) {
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return line_index;
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}
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mask = BIT(line_index);
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config_index = line_index / 8;
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config_shift = (line_index % 8) * 4;
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/* Lock everything so it's safe to reconfigure */
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key = irq_lock();
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/* Disable the EIC for reconfiguration */
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set_eic_enable(0);
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line_assignment = &dev_data->lines[line_index];
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/* Check that the required line is available */
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if (line_assignment->enabled) {
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if (line_assignment->port != port ||
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line_assignment->pin != pin) {
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goto err_in_use;
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}
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}
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/* Set the EIC configuration data */
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port_data = &dev_data->ports[port];
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port_data->cb = cb;
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port_data->data = data;
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line_assignment->pin = pin;
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line_assignment->port = port;
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line_assignment->enabled = 1;
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config = EIC->CONFIG[config_index].reg;
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config &= ~(0xF << config_shift);
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switch (trigger) {
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case SAM0_EIC_RISING:
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config |= EIC_CONFIG_SENSE0_RISE << config_shift;
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break;
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case SAM0_EIC_FALLING:
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config |= EIC_CONFIG_SENSE0_FALL << config_shift;
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break;
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case SAM0_EIC_BOTH:
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config |= EIC_CONFIG_SENSE0_BOTH << config_shift;
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break;
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case SAM0_EIC_HIGH:
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config |= EIC_CONFIG_SENSE0_HIGH << config_shift;
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break;
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case SAM0_EIC_LOW:
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config |= EIC_CONFIG_SENSE0_LOW << config_shift;
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break;
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}
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if (filter) {
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config |= EIC_CONFIG_FILTEN0 << config_shift;
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}
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/* Apply the config to the EIC itself */
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EIC->CONFIG[config_index].reg = config;
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set_eic_enable(1);
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wait_synchronization();
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/*
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* Errata: The EIC generates a spurious interrupt for the newly
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* enabled pin after being enabled, so clear it before re-enabling
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* the IRQ.
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*/
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EIC->INTFLAG.reg = mask;
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irq_unlock(key);
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return 0;
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err_in_use:
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set_eic_enable(1);
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wait_synchronization();
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irq_unlock(key);
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return -EBUSY;
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}
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static bool sam0_eic_check_ownership(int port, int pin, int line_index)
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{
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const struct device *const dev = DEVICE_DT_INST_GET(0);
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struct sam0_eic_data *dev_data = dev->data;
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struct sam0_eic_line_assignment *line_assignment =
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&dev_data->lines[line_index];
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if (!line_assignment->enabled) {
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return false;
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}
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if (line_assignment->port != port ||
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line_assignment->pin != pin) {
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return false;
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}
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return true;
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}
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int sam0_eic_release(int port, int pin)
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{
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const struct device *const dev = DEVICE_DT_INST_GET(0);
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struct sam0_eic_data *dev_data = dev->data;
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uint32_t mask;
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int line_index;
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int config_index;
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int config_shift;
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unsigned int key;
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line_index = sam0_eic_map_to_line(port, pin);
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if (line_index < 0) {
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return line_index;
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}
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mask = BIT(line_index);
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config_index = line_index / 8;
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config_shift = (line_index % 8) * 4;
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/* Lock everything so it's safe to reconfigure */
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key = irq_lock();
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/* Disable the EIC */
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set_eic_enable(0);
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wait_synchronization();
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/*
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* Check to make sure the requesting actually owns the line and do
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* nothing if it does not.
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*/
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if (!sam0_eic_check_ownership(port, pin, line_index)) {
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goto done;
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}
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dev_data->lines[line_index].enabled = 0;
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/* Clear the EIC config, including the trigger condition */
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EIC->CONFIG[config_index].reg &= ~(0xF << config_shift);
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/* Clear any pending interrupt for it */
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EIC->INTENCLR.reg = mask;
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EIC->INTFLAG.reg = mask;
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done:
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set_eic_enable(1);
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wait_synchronization();
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irq_unlock(key);
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return 0;
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}
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int sam0_eic_enable_interrupt(int port, int pin)
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{
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uint32_t mask;
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int line_index;
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line_index = sam0_eic_map_to_line(port, pin);
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if (line_index < 0) {
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return line_index;
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}
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if (!sam0_eic_check_ownership(port, pin, line_index)) {
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return -EBUSY;
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}
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mask = BIT(line_index);
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EIC->INTFLAG.reg = mask;
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EIC->INTENSET.reg = mask;
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return 0;
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}
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int sam0_eic_disable_interrupt(int port, int pin)
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{
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uint32_t mask;
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int line_index;
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line_index = sam0_eic_map_to_line(port, pin);
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if (line_index < 0) {
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return line_index;
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}
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if (!sam0_eic_check_ownership(port, pin, line_index)) {
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return -EBUSY;
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}
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mask = BIT(line_index);
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EIC->INTENCLR.reg = mask;
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EIC->INTFLAG.reg = mask;
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return 0;
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}
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uint32_t sam0_eic_interrupt_pending(int port)
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{
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const struct device *const dev = DEVICE_DT_INST_GET(0);
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struct sam0_eic_data *dev_data = dev->data;
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struct sam0_eic_line_assignment *line_assignment;
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uint32_t set = EIC->INTFLAG.reg;
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uint32_t mask = 0;
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for (int line_index = 0; line_index < EIC_EXTINT_NUM; line_index++) {
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line_assignment = &dev_data->lines[line_index];
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if (!line_assignment->enabled) {
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continue;
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}
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if (line_assignment->port != port) {
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continue;
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}
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if (!(set & BIT(line_index))) {
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continue;
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}
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mask |= BIT(line_assignment->pin);
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}
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return mask;
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}
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#define SAM0_EIC_IRQ_CONNECT(n) \
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do { \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, n, irq), \
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DT_INST_IRQ_BY_IDX(0, n, priority), \
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sam0_eic_isr, DEVICE_DT_INST_GET(0), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(0, n, irq)); \
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} while (false)
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static int sam0_eic_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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#ifdef MCLK
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/* Enable the EIC clock in APBAMASK */
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MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
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/* Enable the GCLK */
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GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0 |
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GCLK_PCHCTRL_CHEN;
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#else
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/* Enable the EIC clock in PM */
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PM->APBAMASK.bit.EIC_ = 1;
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/* Enable the GCLK */
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN_GCLK0 |
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GCLK_CLKCTRL_CLKEN;
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#endif
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#if DT_INST_IRQ_HAS_CELL(0, irq)
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SAM0_EIC_IRQ_CONNECT(0);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 1)
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SAM0_EIC_IRQ_CONNECT(1);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 2)
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SAM0_EIC_IRQ_CONNECT(2);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 3)
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SAM0_EIC_IRQ_CONNECT(3);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 4)
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SAM0_EIC_IRQ_CONNECT(4);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 5)
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SAM0_EIC_IRQ_CONNECT(5);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 6)
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SAM0_EIC_IRQ_CONNECT(6);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 7)
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SAM0_EIC_IRQ_CONNECT(7);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 8)
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SAM0_EIC_IRQ_CONNECT(8);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 9)
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SAM0_EIC_IRQ_CONNECT(9);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 10)
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SAM0_EIC_IRQ_CONNECT(10);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 11)
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SAM0_EIC_IRQ_CONNECT(11);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 12)
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SAM0_EIC_IRQ_CONNECT(12);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 13)
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SAM0_EIC_IRQ_CONNECT(13);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 14)
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SAM0_EIC_IRQ_CONNECT(14);
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#endif
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#if DT_INST_IRQ_HAS_IDX(0, 15)
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SAM0_EIC_IRQ_CONNECT(15);
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#endif
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set_eic_enable(1);
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wait_synchronization();
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return 0;
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}
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static struct sam0_eic_data eic_data;
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DEVICE_DT_INST_DEFINE(0, sam0_eic_init,
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NULL, &eic_data, NULL,
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PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY,
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NULL);
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