285 lines
7.0 KiB
C
285 lines
7.0 KiB
C
/*
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* Copyright (c) 2020 ITE Corporation. All Rights Reserved
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/init.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(intc_it8xxx2, LOG_LEVEL_DBG);
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#include <zephyr/sys/printk.h>
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#include <zephyr/sw_isr_table.h>
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#include "intc_ite_it8xxx2.h"
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#define MAX_REGISR_IRQ_NUM 8
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#define IVECT_OFFSET_WITH_IRQ 0x10
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/* Interrupt number of INTC module */
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static uint8_t intc_irq;
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static volatile uint8_t *const reg_status[] = {
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&ISR0, &ISR1, &ISR2, &ISR3,
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&ISR4, &ISR5, &ISR6, &ISR7,
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&ISR8, &ISR9, &ISR10, &ISR11,
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&ISR12, &ISR13, &ISR14, &ISR15,
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&ISR16, &ISR17, &ISR18, &ISR19,
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&ISR20, &ISR21, &ISR22, &ISR23
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};
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static volatile uint8_t *const reg_enable[] = {
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&IER0, &IER1, &IER2, &IER3,
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&IER4, &IER5, &IER6, &IER7,
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&IER8, &IER9, &IER10, &IER11,
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&IER12, &IER13, &IER14, &IER15,
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&IER16, &IER17, &IER18, &IER19,
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&IER20, &IER21, &IER22, &IER23
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};
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/* edge/level trigger register */
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static volatile uint8_t *const reg_ielmr[] = {
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&IELMR0, &IELMR1, &IELMR2, &IELMR3,
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&IELMR4, &IELMR5, &IELMR6, &IELMR7,
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&IELMR8, &IELMR9, &IELMR10, &IELMR11,
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&IELMR12, &IELMR13, &IELMR14, &IELMR15,
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&IELMR16, &IELMR17, &IELMR18, &IELMR19,
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&IELMR20, &IELMR21, &IELMR22, &IELMR23,
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};
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/* high/low trigger register */
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static volatile uint8_t *const reg_ipolr[] = {
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&IPOLR0, &IPOLR1, &IPOLR2, &IPOLR3,
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&IPOLR4, &IPOLR5, &IPOLR6, &IPOLR7,
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&IPOLR8, &IPOLR9, &IPOLR10, &IPOLR11,
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&IPOLR12, &IPOLR13, &IPOLR14, &IPOLR15,
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&IPOLR16, &IPOLR17, &IPOLR18, &IPOLR19,
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&IPOLR20, &IPOLR21, &IPOLR22, &IPOLR23
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};
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#define IT8XXX2_IER_COUNT ARRAY_SIZE(reg_enable)
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static uint8_t ier_setting[IT8XXX2_IER_COUNT];
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void ite_intc_save_and_disable_interrupts(void)
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{
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volatile uint8_t _ier __unused;
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/* Disable global interrupt for critical section */
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unsigned int key = irq_lock();
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/* Save and disable interrupts */
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for (int i = 0; i < IT8XXX2_IER_COUNT; i++) {
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ier_setting[i] = *reg_enable[i];
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*reg_enable[i] = 0;
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}
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/*
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* This load operation will guarantee the above modification of
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* SOC's register can be seen by any following instructions.
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* Note: Barrier instruction can not synchronize chip register,
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* so we introduce workaround here.
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*/
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_ier = *reg_enable[IT8XXX2_IER_COUNT - 1];
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irq_unlock(key);
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}
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void ite_intc_restore_interrupts(void)
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{
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/*
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* Ensure the highest priority interrupt will be the first fired
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* interrupt when soc is ready to go.
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*/
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unsigned int key = irq_lock();
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/* Restore interrupt state */
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for (int i = 0; i < IT8XXX2_IER_COUNT; i++) {
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*reg_enable[i] = ier_setting[i];
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}
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irq_unlock(key);
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}
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void ite_intc_isr_clear(unsigned int irq)
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{
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uint32_t g, i;
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volatile uint8_t *isr;
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if (irq > CONFIG_NUM_IRQS) {
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return;
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}
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g = irq / MAX_REGISR_IRQ_NUM;
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i = irq % MAX_REGISR_IRQ_NUM;
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isr = reg_status[g];
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*isr = BIT(i);
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}
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void __soc_ram_code ite_intc_irq_enable(unsigned int irq)
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{
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uint32_t g, i;
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volatile uint8_t *en;
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if (irq > CONFIG_NUM_IRQS) {
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return;
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}
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g = irq / MAX_REGISR_IRQ_NUM;
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i = irq % MAX_REGISR_IRQ_NUM;
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en = reg_enable[g];
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/* critical section due to run a bit-wise OR operation */
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unsigned int key = irq_lock();
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SET_MASK(*en, BIT(i));
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irq_unlock(key);
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}
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void __soc_ram_code ite_intc_irq_disable(unsigned int irq)
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{
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uint32_t g, i;
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volatile uint8_t *en;
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volatile uint8_t _ier __unused;
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if (irq > CONFIG_NUM_IRQS) {
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return;
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}
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g = irq / MAX_REGISR_IRQ_NUM;
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i = irq % MAX_REGISR_IRQ_NUM;
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en = reg_enable[g];
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/* critical section due to run a bit-wise OR operation */
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unsigned int key = irq_lock();
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CLEAR_MASK(*en, BIT(i));
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/*
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* This load operation will guarantee the above modification of
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* SOC's register can be seen by any following instructions.
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*/
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_ier = *en;
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irq_unlock(key);
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}
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void ite_intc_irq_polarity_set(unsigned int irq, unsigned int flags)
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{
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uint32_t g, i;
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volatile uint8_t *tri;
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if ((irq > CONFIG_NUM_IRQS) || ((flags&IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)) {
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return;
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}
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g = irq / MAX_REGISR_IRQ_NUM;
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i = irq % MAX_REGISR_IRQ_NUM;
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tri = reg_ipolr[g];
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if ((flags&IRQ_TYPE_LEVEL_HIGH) || (flags&IRQ_TYPE_EDGE_RISING)) {
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CLEAR_MASK(*tri, BIT(i));
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} else {
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SET_MASK(*tri, BIT(i));
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}
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tri = reg_ielmr[g];
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if ((flags&IRQ_TYPE_LEVEL_LOW) || (flags&IRQ_TYPE_LEVEL_HIGH)) {
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CLEAR_MASK(*tri, BIT(i));
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} else {
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SET_MASK(*tri, BIT(i));
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}
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}
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int __soc_ram_code ite_intc_irq_is_enable(unsigned int irq)
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{
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uint32_t g, i;
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volatile uint8_t *en;
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if (irq > CONFIG_NUM_IRQS) {
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return 0;
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}
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g = irq / MAX_REGISR_IRQ_NUM;
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i = irq % MAX_REGISR_IRQ_NUM;
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en = reg_enable[g];
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return IS_MASK_SET(*en, BIT(i));
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}
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uint8_t __soc_ram_code ite_intc_get_irq_num(void)
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{
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return intc_irq;
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}
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bool __soc_ram_code ite_intc_no_irq(void)
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{
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return (IVECT == IVECT_OFFSET_WITH_IRQ);
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}
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uint8_t __soc_ram_code get_irq(void *arg)
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{
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ARG_UNUSED(arg);
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/* wait until two equal interrupt values are read */
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do {
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/* Read interrupt number from interrupt vector register */
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intc_irq = IVECT;
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/*
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* WORKAROUND: when the interrupt vector register (IVECT)
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* isn't latched in a load operation, we read it again to make
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* sure the value we got is the correct value.
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*/
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} while (intc_irq != IVECT);
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/* determine interrupt number */
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intc_irq -= IVECT_OFFSET_WITH_IRQ;
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/*
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* Look for pending interrupt if there's interrupt number 0 from
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* the AIVECT register.
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*/
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if (intc_irq == 0) {
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uint8_t int_pending;
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for (int i = (IT8XXX2_IER_COUNT - 1); i >= 0; i--) {
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int_pending = (*reg_status[i] & *reg_enable[i]);
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if (int_pending != 0) {
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intc_irq = (MAX_REGISR_IRQ_NUM * i) +
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find_msb_set(int_pending) - 1;
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LOG_DBG("Pending interrupt found: %d",
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intc_irq);
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LOG_DBG("CPU mepc: 0x%lx", csr_read(mepc));
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break;
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}
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}
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}
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/* clear interrupt status */
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ite_intc_isr_clear(intc_irq);
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/* return interrupt number */
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return intc_irq;
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}
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void soc_interrupt_init(void)
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{
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#ifdef CONFIG_ZTEST
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/*
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* After flashed EC image, we needed to manually press the reset button
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* on it8xxx2_evb, then run the test. Now, without pressing the button,
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* we can disable debug mode and trigger a watchdog hard reset then
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* run tests.
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*/
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struct wdt_it8xxx2_regs *const wdt_regs = WDT_IT8XXX2_REGS_BASE;
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struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
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if (gctrl_regs->GCTRL_DBGROS & IT8XXX2_GCTRL_SMB_DBGR) {
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/* Disable debug mode through i2c */
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IT8XXX2_SMB_SLVISELR |= BIT(4);
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/* Enable ETWD reset */
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wdt_regs->ETWCFG = 0;
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wdt_regs->ET1PSR = IT8XXX2_WDT_ETPS_1P024_KHZ;
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wdt_regs->ETWCFG = (IT8XXX2_WDT_EWDKEYEN | IT8XXX2_WDT_EWDSRC);
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/* Enable ETWD hardware reset */
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gctrl_regs->GCTRL_ETWDUARTCR |= IT8XXX2_GCTRL_ETWD_HW_RST_EN;
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/* Trigger ETWD reset */
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wdt_regs->EWDKEYR = 0;
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/* Spin and wait for reboot */
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while (1)
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;
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} else {
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/* Disable ETWD hardware reset */
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gctrl_regs->GCTRL_ETWDUARTCR &= ~IT8XXX2_GCTRL_ETWD_HW_RST_EN;
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}
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#endif
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/* Ensure interrupts of soc are disabled at default */
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for (int i = 0; i < ARRAY_SIZE(reg_enable); i++) {
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*reg_enable[i] = 0;
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}
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/* Enable M-mode external interrupt */
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csr_set(mie, MIP_MEIP);
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}
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