362 lines
4.8 KiB
C
362 lines
4.8 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_RF_H_
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#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_RF_H_
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#include <zephyr/drivers/ieee802154/cc1200.h>
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#define CC1200_RF_NON_EXT_SPACE_REGS 42
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#define CC1200_RF_EXT_SPACE_REGS 58
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/* About PKTCFGn from Kconfig:
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* CONFIG_IEEE802154_CC1200_PKTCFG0 LENGTH_VAR_1
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* CONFIG_IEEE802154_CC1200_PKTCFG1 (APPEND_STATUS | CRC_FFFF | ADDR_NO_CHK)
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* We do not enable 802.15.4g mode yet:
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* CONFIG_IEEE802154_CC1200_PKTCFG2 (PKT_FORMAT_NORMAL_MODE | CCA_ALWAYS_CLEAR)
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**/
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#ifdef CONFIG_IEEE802154_CC1200_RF_PRESET
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#if defined(CONFIG_IEEE802154_CC1200_RF_SET_0)
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#define IEEE802154_CC1200_CHANNEL_LIMIT 33
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const struct cc1200_rf_registers_set cc1200_rf_settings = {
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.chan_center_freq0 = 863125,
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.channel_spacing = 2000, /* 200 KHz */
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.registers = {
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0x6F, /* SYNC3 */
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0x4E,
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0x90,
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0x4E,
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0xE5,
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0x23,
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0x47,
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0x0B,
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0x56,
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0x19, /* 0x14 */
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0xBA,
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0xC8,
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0x84,
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0x42,
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0x05,
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0x94,
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0x7A,
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0xE1,
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0x27,
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CONFIG_IEEE802154_CC1200_CCA_THRESHOLD,
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CONFIG_IEEE802154_CC1200_RSSI_OFFSET,
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0xB1,
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0x20,
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0x11,
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0x90,
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0x00,
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0x00,
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CONFIG_IEEE802154_CC1200_SETTLING_CFG,
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0x12,
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0x08,
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0x21,
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0x00,
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0x00,
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0x00,
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CONFIG_IEEE802154_CC1200_PKTCFG2,
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CONFIG_IEEE802154_CC1200_PKTCFG1,
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CONFIG_IEEE802154_CC1200_PKTCFG0,
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CONFIG_IEEE802154_CC1200_RFEND_CFG1,
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CONFIG_IEEE802154_CC1200_RFEND_CFG0,
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0x7F,
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0x56,
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0x0F, /* ASK_CFG */
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0x18, /* IF_MIX_CFG */
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0x20,
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0x03,
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0x00,
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0x00,
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0x02,
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0x01,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x56,
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0xCC,
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0xCC,
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0x02,
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0xEE,
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0x10,
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0x04,
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0x50,
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0x00,
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0x20,
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0x40,
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0x0E,
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0x28,
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0x03,
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0x00,
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0x33,
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0xF7,
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0x0F,
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0x00,
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0x00,
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0x6E,
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0x1C,
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0xAC,
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0x14,
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0x00,
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0x00,
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0x00,
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0xB5,
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0x00,
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0x02,
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0x00,
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0x00,
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0x10,
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0x00,
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0x00,
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0x05,
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0x01,
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0x01,
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0x0E,
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0xA0,
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0x03,
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0x04,
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0x03,
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0x00,
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0x00,
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0x00, /* PA_CFG3 */
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}
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};
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#elif defined(CONFIG_IEEE802154_CC1200_RF_SET_1)
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#define IEEE802154_CC1200_CHANNEL_LIMIT 38
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const struct cc1200_rf_registers_set cc1200_rf_settings = {
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.chan_center_freq0 = 920600,
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.channel_spacing = 2000, /* 200 KHz */
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.registers = {
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0x6F, /* SYNC3 */
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0x4E,
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0x90,
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0x4E,
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0xE5,
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0x23,
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0x47,
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0x0B,
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0x56,
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0x14,
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0xBA,
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0xC8,
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0x84,
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0x42,
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0x05,
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0x94,
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0x7A,
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0xE1,
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0x27,
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CONFIG_IEEE802154_CC1200_CCA_THRESHOLD,
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CONFIG_IEEE802154_CC1200_RSSI_OFFSET,
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0xB1,
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0x20,
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0x11,
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0x90,
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0x00,
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0x00,
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CONFIG_IEEE802154_CC1200_SETTLING_CFG,
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0x12,
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0x08,
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0x21,
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0x00,
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0x00,
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0x00,
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CONFIG_IEEE802154_CC1200_PKTCFG2,
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CONFIG_IEEE802154_CC1200_PKTCFG1,
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CONFIG_IEEE802154_CC1200_PKTCFG0,
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CONFIG_IEEE802154_CC1200_RFEND_CFG1,
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CONFIG_IEEE802154_CC1200_RFEND_CFG0
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0x7F,
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0x56,
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0x0F, /* ASK_CFG */
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0x18, /* IF_MIX_CFG */
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0x20,
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0x03,
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0x00,
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0x00,
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0x02,
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0x01,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x5C,
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0x0F,
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0x5C,
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0x02,
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0xEE,
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0x10,
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0x04,
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0x55,
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0x00,
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0x20,
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0x40,
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0x0E,
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0x28,
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0x03,
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0x00,
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0x33,
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0xFF,
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0x17,
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0x00,
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0x00,
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0x6E,
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0x1C,
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0xAC,
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0x14,
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0x00,
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0x00,
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0x00,
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0xB5,
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0x00,
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0x02,
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0x00,
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0x00,
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0x10,
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0x00,
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0x00,
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0x05,
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0x01,
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0x01,
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0x0E,
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0xA0,
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0x03,
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0x04,
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0x03,
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0x00,
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0x00,
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0x00, /* PA_CFG3 */
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}
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};
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#elif defined(CONFIG_IEEE802154_CC1200_RF_SET_2)
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#define IEEE802154_CC1200_CHANNEL_LIMIT 14
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const struct cc1200_rf_registers_set cc1200_rf_settings = {
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.chan_center_freq0 = 433164,
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.channel_spacing = 2000, /* 200 KHz */
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.registers = {
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0x6F, /* SYNC3 */
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0x4E,
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0x90,
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0x4E,
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0xE5,
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0x23,
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0x47,
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0x0B,
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0x56,
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0x14,
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0xBA,
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0xC8,
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0x84,
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0x42,
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0x05,
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0x94,
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0x7A,
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0xE1,
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0x27,
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CONFIG_IEEE802154_CC1200_CCA_THRESHOLD,
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CONFIG_IEEE802154_CC1200_RSSI_OFFSET,
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0xB1,
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0x20,
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0x11,
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0x90,
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0x00,
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0x00,
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CONFIG_IEEE802154_CC1200_SETTLING_CFG,
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0x14,
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0x08,
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0x21,
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0x00,
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0x00,
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0x00,
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CONFIG_IEEE802154_CC1200_PKTCFG2,
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CONFIG_IEEE802154_CC1200_PKTCFG1,
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CONFIG_IEEE802154_CC1200_PKTCFG0,
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CONFIG_IEEE802154_CC1200_RFEND_CFG1,
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CONFIG_IEEE802154_CC1200_RFEND_CFG0,
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0x7F,
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0x56,
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0x0F, /* ASK_CFG */
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0x18, /* IF_MIX_CFG */
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0x20,
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0x03,
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0x00,
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0x00,
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0x02,
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0x01,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x56,
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0xCC,
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0xCC,
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0x02,
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0xEE,
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0x10,
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0x04,
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0x50,
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0x00,
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0x20,
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0x40,
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0x0E,
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0x28,
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0x03,
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0x00,
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0x33,
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0xF7,
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0x0F,
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0x00,
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0x00,
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0x6E,
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0x1C,
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0xAC,
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0x14,
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0x00,
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0x00,
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0x00,
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0xB5,
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0x00,
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0x02,
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0x00,
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0x00,
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0x10,
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0x00,
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0x00,
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0x05,
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0x01,
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0x01,
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0x0E,
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0xA0,
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0x03,
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0x04,
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0x03,
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0x00,
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0x00,
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0x00, /* PA_CFG3 */
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}
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};
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#endif /* CONFIG_IEEE802154_CC1200_RF_SET_n */
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#endif /* CONFIG_IEEE802154_CC1200_RF_PRESET */
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#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_RF_H_ */
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